From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B80E14FCE5; Tue, 16 Jan 2024 19:58:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705435129; cv=none; b=qa/++fCZLmf7XezfgxeFsYQvrdmSYL7rtfMiotl5HVBUaj0Vilr3Tzua+UIi5YNsQluggoNXrtX4Yr+VItWhgLzOUajKTr0rX6yiaolVQEzzMlv0dg8teKqkwEcBo1imiz3eEVuqhDsNPPr35sj1BXUhDpK4aoAE2v2M13bHHQA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705435129; c=relaxed/simple; bh=RIzj2FCb0MYZlbM3iGqpMEKR+6Z7dJtJ9BbMuo+nP78=; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID: X-Mailer:In-Reply-To:References:MIME-Version:X-stable: X-Patchwork-Hint:X-stable-base:Content-Transfer-Encoding; b=JfcjC4nkGdNXI4x3DzWVQ4OoFwLWn+4bc00oqHbsa84vCXL+KTDC3Zb7zzZcQNGvS4gdnzj2SSoHUbKau7CWa3+qrRXY9+E49vKv0uyQ9894zkmLDNKnWgIzdhqIsBJHIKLtY9FSfYl4uNIOMHSBVJn6LvDsNLA9VJL95VbaJt4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PYdmCF3a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PYdmCF3a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7CB40C433F1; Tue, 16 Jan 2024 19:58:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1705435129; bh=RIzj2FCb0MYZlbM3iGqpMEKR+6Z7dJtJ9BbMuo+nP78=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PYdmCF3aadgVrM8Ge7FF8QNe/iWn2hkasT9Iznf2v4ZBvO88Ebv0yeIa0e69nEKtx Kikynh7CI5F5+Dd2e718C0wHDGJw0dRV4GoXrQjjxdwZStnvXMTMDGhFPkXBlawkqb d5LKnuoTYB3qiD03wBYn0GPO0x8DLvuZtm6H92sAYkMF3ImBeQuDGJ/aiURG97oXgk dVvFIs2cD/za1k09WcLamlWXJz2fSmj2d1rTH8abCxSisbqJzpPioEqTM8C1s1IcrH hMWgUuJ3eLXyDAdduSjhLNVHODsqZWJcd76bBbKgBkHqwMHXCZz5wz9P0iLAHaeRYW 2xKyl/bg4hQtg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ido Schimmel , Bjorn Helgaas , Petr Machata , "David S . Miller" , Sasha Levin , linux-pci@vger.kernel.org Subject: [PATCH AUTOSEL 5.15 06/47] PCI: Add no PM reset quirk for NVIDIA Spectrum devices Date: Tue, 16 Jan 2024 14:57:09 -0500 Message-ID: <20240116195834.257313-6-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240116195834.257313-1-sashal@kernel.org> References: <20240116195834.257313-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 5.15.147 Content-Transfer-Encoding: 8bit From: Ido Schimmel [ Upstream commit 3ed48c80b28d8dcd584d6ddaf00c75b7673e1a05 ] Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset (i.e., they advertise NoSoftRst-). However, this transition does not have any effect on the device: It continues to be operational and network ports remain up. Advertising this support makes it seem as if a PM reset is viable for these devices. Mark it as unavailable to skip it when testing reset methods. Before: # cat /sys/bus/pci/devices/0000\:03\:00.0/reset_method pm bus After: # cat /sys/bus/pci/devices/0000\:03\:00.0/reset_method bus Signed-off-by: Ido Schimmel Acked-by: Bjorn Helgaas Signed-off-by: Petr Machata Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/pci/quirks.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 5d8768cd7c50..0b6aae333f5a 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3666,6 +3666,19 @@ static void quirk_no_pm_reset(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); +/* + * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset + * (i.e., they advertise NoSoftRst-). However, this transition does not have + * any effect on the device: It continues to be operational and network ports + * remain up. Advertising this support makes it seem as if a PM reset is viable + * for these devices. Mark it as unavailable to skip it when testing reset + * methods. + */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); + /* * Thunderbolt controllers with broken MSI hotplug signaling: * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part -- 2.43.0