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Wed, 31 Jan 2024 22:40:44 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id y9-20020aa79e09000000b006ddc7af02c1sm10925764pfq.9.2024.01.31.22.40.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 22:40:44 -0800 (PST) From: Charlie Jenkins Subject: [PATCH 0/2] riscv: Use CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS to set misaligned access speed Date: Wed, 31 Jan 2024 22:40:21 -0800 Message-Id: <20240131-disable_misaligned_probe_config-v1-0-98d155e9cda8@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIANU8u2UC/x2N0QqEIBQFfyXu8wqaRWy/EotYHu1Cq6EQQfTvS U/DvMxcVJAZhcbmooyDC6dYRX0aWlYbAwS76tTKtpNKK+G42HmD+VduHCKc2XOaYZYUPQchO21 h9dD7r6Za2TM8n+9h+t33A0h4BwdxAAAA To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Jisheng Zhang , Evan Green Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706769643; l=1017; i=charlie@rivosinc.com; s=20231120; h=from:subject:message-id; bh=0A0EZZ7L95Ss35itIndFIHG4J0n0kRMyQ0DhF7dwS5s=; b=SeGBVfFBkE4J7EYJovzsM69HMfy3aak+n9KCMy69XDFTQYJ7A+C6YXRsFT36I1J3p8NOCVMv5 ak3R0x0n060C/9eGi+WkN7w7629bYXVojTs1C8/8+7zKwdX1PqCEdtQ X-Developer-Key: i=charlie@rivosinc.com; a=ed25519; pk=t4RSWpMV1q5lf/NWIeR9z58bcje60/dbtxxmoSfBEcs= If CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is enabled, no time needs to be spent in the misaligned access speed probe. Disable the probe in this case and set respective uses to "fast" misaligned accesses. On riscv, this config is selected if RISCV_EFFICIENT_UNALIGNED_ACCESS is selected, which is dependent on NONPORTABLE. Signed-off-by: Charlie Jenkins --- Charlie Jenkins (2): riscv: lib: Introduce has_fast_misaligned_access function riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS arch/riscv/include/asm/cpufeature.h | 13 +++++++++++++ arch/riscv/kernel/cpufeature.c | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ arch/riscv/kernel/traps_misaligned.c | 4 ++++ arch/riscv/lib/csum.c | 5 +---- 5 files changed, 26 insertions(+), 4 deletions(-) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240131-disable_misaligned_probe_config-043aea375f93 -- - Charlie