From: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
To: patrick@stwcx.xyz, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@codeconstruct.com.au>
Cc: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state
Date: Wed, 31 Jan 2024 16:41:27 +0800 [thread overview]
Message-ID: <20240131084134.328307-17-Delphine_CC_Chiu@wiwynn.com> (raw)
In-Reply-To: <20240131084134.328307-1-Delphine_CC_Chiu@wiwynn.com>
Initialize bmc gpio state
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
Changelog:
- v4
- Rename gpio-line-names
- v3
- Add patch for revising gpio name
---
.../aspeed/aspeed-bmc-facebook-yosemite4.dts | 192 ++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 6d5710e5753c..bce739f2a081 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -1271,6 +1271,7 @@ temperature-sensor@1f {
};
};
+
&adc0 {
ref_voltage = <2500>;
status = "okay";
@@ -1298,3 +1299,194 @@ &ehci1 {
&uhci {
status = "okay";
};
+
+&sgpiom0 {
+ status = "okay";
+ ngpios = <128>;
+ bus-frequency = <48000>;
+};
+
+&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiu2_default &pinctrl_gpiu3_default
+ &pinctrl_gpiu4_default &pinctrl_gpiu6_default>;
+ gpio-line-names =
+ /*A0-A7*/ "","","","","","","","",
+ /*B0-B7*/ "FLT-HSC-SERVER-SLOT8-N","AC-ON-OFF-BTN-CPLD-SLOT5-N",
+ "PWRGD-SLOT1-STBY","PWRGD-SLOT2-STBY",
+ "PWRGD-SLOT3-STBY","PWRGD-SLOT4-STBY","","",
+ /*C0-C7*/ "","","","","FM-NIC0-WAKE-N",
+ "FM-NIC1-WAKE-N","","RST-PCIE-SLOT2-N",
+ /*D0-D7*/ "","","","","","","","",
+ /*E0-E7*/ "PRSNT-NIC1-N","PRSNT-NIC2-N","","RST-PCIE-SLOT1-N",
+ "","","","",
+ /*F0-F7*/ "FM-RESBTN-SLOT1-BMC-N","FM-RESBTN-SLOT2-BMC-N",
+ "FM-RESBTN-SLOT3-BMC-N","FM-RESBTN-SLOT4-BMC-N",
+ "PRSNT-SB-SLOT1-N","PRSNT-SB-SLOT2-N",
+ "PRSNT-SB-SLOT3-N","PRSNT-SB-SLOT4-N",
+ /*G0-G7*/ "","","","","","","","",
+ /*H0-H7*/ "","","","","","","","",
+ /*I0-I7*/ "","","","","","ALT-MEDUSA-ADC-N",
+ "ALT-SMB-BMC-CPLD2-N",
+ "INT-SPIDER-ADC-R-N",
+ /*J0-J7*/ "","","","","","","","",
+ /*K0-K7*/ "","","","","","","","",
+ /*L0-L7*/ "","","","","","","ALT-MEDUSA-P12V-EFUSE-N","",
+ /*M0-M7*/ "EN-NIC0-POWER-BMC-R","EN-NIC1-POWER-BMC-R",
+ "INT-MEDUSA-IOEXP-TEMP-N","PRSNT-NIC3-N",
+ "INT-SMB-BMC-SLOT1-4-BMC-N",
+ "AC-ON-OFF-BTN-CPLD-SLOT6-N","","",
+ /*N0-N7*/ "FLT-HSC-SERVER-SLOT1-N","FLT-HSC-SERVER-SLOT2-N",
+ "FLT-HSC-SERVER-SLOT3-N","FLT-HSC-SERVER-SLOT4-N",
+ "FM-BMC-READY-R2","RST-SMB-NIC0-R-N","","",
+ /*O0-O7*/ "AC-ON-OFF-BTN-CPLD-SLOT8-N","RST-SMB-NIC1-R-N",
+ "RST-SMB-NIC2-R-N","RST-SMB-NIC3-R-N",
+ "","","","",
+ /*P0-P7*/ "ALT-SMB-BMC-CPLD1-N","'BTN-BMC-R2-N",
+ "EN-P3V-BAT-SCALED-R","PWRGD-P5V-USB-BMC",
+ "FM-BMC-RTCRST-R","RST-USB-HUB-R-N",
+ "FLAG-P5V-USB-BMC-N","",
+ /*Q0-Q7*/ "AC-ON-OFF-BTN-CPLD-SLOT1-N","AC-ON-OFF-BTN-CPLD-SLOT2-N",
+ "AC-ON-OFF-BTN-CPLD-SLOT3-N","AC-ON-OFF-BTN-CPLD-SLOT4-N",
+ "PRSNT-SB-SLOT5-N","PRSNT-SB-SLOT6-N",
+ "PRSNT-SB-SLOT7-N","PRSNT-SB-SLOT8-N",
+ /*R0-R7*/ "AC-ON-OFF-BTN-CPLD-SLOT7-N","INT-SMB-BMC-SLOT5-8-BMC-N",
+ "FM-PWRBRK-NIC-BMC-R2","RST-PCIE-SLOT4-N",
+ "RST-PCIE-SLOT5-N","RST-PCIE-SLOT6-N",
+ "RST-PCIE-SLOT7-N","RST-PCIE-SLOT8-N",
+ /*S0-S7*/ "FM-NIC2-WAKE-N","FM-NIC3-WAKE-N",
+ "EN-NIC3-POWER-BMC-R","SEL-BMC-JTAG-MUX-R",
+ "","ALT-P12V-AUX-N","FAST-PROCHOT-N",
+ "SPI-WP-DISABLE-STATUS-R-N",
+ /*T0-T7*/ "","","","","","","","",
+ /*U0-U7*/ "","","RST-PCIE-SLOT3-N","",
+ "","PRSNT-NIC0-N","","",
+ /*V0-V7*/ "FM-RESBTN-SLOT5-BMC-N","FM-RESBTN-SLOT6-BMC-N",
+ "FM-RESBTN-SLOT7-BMC-N","FM-RESBTN-SLOT8-BMC-N",
+ "","","","",
+ /*W0-W7*/ "PRSNT-TPM-BMC-N","PRSNT-OCP-DEBUG-BMC-N","ALT-TEMP-BMC-N","ALT-RTC-BMC-N",
+ "","","","",
+ /*X0-X7*/ "","LT-HSC-SERVER-SLOT6-N","FLT-HSC-SERVER-SLOT7-N","","","",
+ "PWRGD-SLOT5-STBY","PWRGD-SLOT6-STBY",
+ /*Y0-Y7*/ "","","SPI-LOCK-REQ-BMC-N","PWRGD-SLOT7-STBY",
+ "","","EN-NIC2-POWER-BMC-R","",
+ /*Z0-Z7*/ "EN-P5V-USB-CPLD-R","'FLT-HSC-SERVER-SLOT5-N",
+ "PWRGD-SLOT8-STBY","","","","","";
+
+ pin_gpio_b4 {
+ gpios = <ASPEED_GPIO(B, 4) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_b5 {
+ gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
+ input;
+ };
+ pin_gpio_f0 {
+ gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f1 {
+ gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f2 {
+ gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f3 {
+ gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f4 {
+ gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f5 {
+ gpios = <ASPEED_GPIO(F, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f6 {
+ gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_f7 {
+ gpios = <ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l6 {
+ gpios = <ASPEED_GPIO(L, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_l7 {
+ gpios = <ASPEED_GPIO(L, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s0 {
+ gpios = <ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_s1 {
+ gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v0 {
+ gpios = <ASPEED_GPIO(V, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v1 {
+ gpios = <ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v2 {
+ gpios = <ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_v3 {
+ gpios = <ASPEED_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w0 {
+ gpios = <ASPEED_GPIO(W, 0) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w1 {
+ gpios = <ASPEED_GPIO(W, 1) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w2 {
+ gpios = <ASPEED_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w3 {
+ gpios = <ASPEED_GPIO(W, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w4 {
+ gpios = <ASPEED_GPIO(W, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w5 {
+ gpios = <ASPEED_GPIO(W, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w6 {
+ gpios = <ASPEED_GPIO(W, 6) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_w7 {
+ gpios = <ASPEED_GPIO(W, 7) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z3 {
+ gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z4 {
+ gpios = <ASPEED_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ input;
+ };
+ pin_gpio_z5 {
+ gpios = <ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
+ input;
+ };
+};
--
2.25.1
next prev parent reply other threads:[~2024-01-31 8:42 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-31 8:41 [PATCH v5 00/21] Add i2c-mux and eeprom devices for Meta Yosemite 4 Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 01/21] ARM: dts: aspeed: yosemite4: Revise i2c-mux devices Delphine CC Chiu
2024-02-01 3:46 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 02/21] ARM: dts: aspeed: yosemite4: Enable adc15 Delphine CC Chiu
2024-02-01 4:13 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 03/21] ARM: dts: aspeed: yosemite4: Enable spi-gpio setting Delphine CC Chiu
2024-02-01 4:15 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 04/21] ARM: dts: aspeed: yosemite4: Enable watchdog2 Delphine CC Chiu
2024-02-01 5:34 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 05/21] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode Delphine CC Chiu
2024-02-01 4:22 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 06/21] ARM: dts: aspeed: yosemite4: Revise power sensor adm1281 for schematic change Delphine CC Chiu
2024-02-01 4:24 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 07/21] ARM: dts: aspeed: yosemite4: Add gpio pca9506 Delphine CC Chiu
2024-02-01 5:35 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 08/21] ARM: dts: aspeed: yosemite4: Remove space for adm1272 compatible Delphine CC Chiu
2024-02-01 4:28 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 09/21] ARM: dts: aspeed: yosemite4: Enable interrupt setting for pca9555 Delphine CC Chiu
2024-02-01 4:33 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 10/21] ARM: dts: aspeed: yosemite4: Add power sensor for power module reading Delphine CC Chiu
2024-02-01 4:34 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 11/21] ARM: dts: aspeed: yosemite4: Add eeprom for yosemite4 use Delphine CC Chiu
2024-02-01 5:45 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 12/21] ARM: dts: aspeed: yosemite4: Remove temperature sensor for yosemite4 schematic change Delphine CC Chiu
2024-02-01 5:38 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 13/21] ARM: dts: aspeed: yosemite4: Revise adc128d818 adc mode " Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 14/21] ARM: dts: aspeed: yosemite4: Revise ina233 config " Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 15/21] ARM: dts: aspeed: yosemite4: Remove idle state setting for yosemite4 NIC connection Delphine CC Chiu
2024-02-01 5:47 ` Andrew Jeffery
2024-01-31 8:41 ` Delphine CC Chiu [this message]
2024-02-01 5:49 ` [PATCH v5 16/21] ARM: dts: aspeed: yosemite4: Initialize bmc gpio state Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 17/21] ARM: dts: aspeed: yosemite4: Revise mx31790 fan tach config Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 18/21] ARM: dts: aspeed: yosemite4: add mctp config for NIC Delphine CC Chiu
2024-02-01 5:53 ` Andrew Jeffery
2024-01-31 8:41 ` [PATCH v5 19/21] ARM: dts: aspeed: yosemite4: support mux to cpld Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 20/21] ARM: dts: aspeed: yosemite4: support medusa board adc sensors Delphine CC Chiu
2024-01-31 8:41 ` [PATCH v5 21/21] ARM: dts: aspeed: yosemite4: support NIC eeprom Delphine CC Chiu
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