From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 704A361667 for ; Tue, 13 Feb 2024 21:04:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858244; cv=none; b=cpgkKVggEaeksZmWYX0KWC6FUcc/mF+lFRiPjKV3LegjQDhFd5r3oNxP2gH4fqBRE9iyfxDIE/X+ZEWOdQ+B7kCPK0UynwvvO6KPChsbDnIo4a/bn52TeUhv7x47gbrt30hV5CVq40SJqJJMYMXpYveJY4Ik1VVjffRzPha7VDA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707858244; c=relaxed/simple; bh=NsdvmTXdQOEAcTe8BH4orT/Rt3CQ5Hp6MYfQha9qhRw=; h=Message-ID:From:To:Cc:Subject:References:MIME-Version: Content-Type:Date; b=WlNay15wEjIscWHkhdFWPC32At6z6eHDMtkEnjEy0vZISi2eYXAFnUEluD7bfXbaOfha7ud55CZIltrBwZONucgCoeUbobTpfXH7aiAKgcwWuE8gAtrR/r310ycRMiuzG1Up5FW+04lEO0SWVy//wopL4L95RXdSD6bVUe5IRCo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WJZpU80A; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bjtaT4nt; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WJZpU80A"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bjtaT4nt" Message-ID: <20240212153624.516965279@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1707858240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=POkOPr2xnUjR9qaFo3XT8NSa9LY45PY9NSX9q3xq04M=; b=WJZpU80AM+0zTcisR+tQshP4J32JDsv0HJxayl6DhfkXVNYJWDEYUxPozZHsVpIt6s7wJg Ny3NZVpIbzMl8Cbzin397wrUz3Tha166670s5fpzGIgRVoZh2yrmIgLYxQlGVgkgZ0hEZb 01xgNm6KxVQCLwSWNUNuH7A/7YoJ+RregUJXaDWtLUnBaGs8oAqU+iJmFWdXvIA3aKLWFQ 9CGjomTB8HEV/Zuq5Gks5Pg7yDE57XM5OPOlFhZyLx97qd8afV2yLIvG7F1vOPQdK99BoE 3yrIfnB9hRLesrqeyZ+dlV9YLJ5bsN6ErpXOGrJORjVkwHoWx6q6oZnqn/8qTA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1707858240; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=POkOPr2xnUjR9qaFo3XT8NSa9LY45PY9NSX9q3xq04M=; b=bjtaT4ntD5roAOEKcqJx5a2m43epaxATRzOPSRT8ELBv7ps3lxctmWaxVTwEPJ0gabEuxy C/V2Gw+NAZkAm6Cg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Tom Lendacky , Andrew Cooper , Arjan van de Ven , Huang Rui , Juergen Gross , Dimitri Sivanich , Sohil Mehta , K Prateek Nayak , Kan Liang , Zhang Rui , "Paul E. McKenney" , Feng Tang , Andy Shevchenko , Michael Kelley , "Peter Zijlstra (Intel)" , Wang Wendy Subject: [patch V6 01/19] x86/cpu: Provide cpuid_read() et al. References: <20240212153109.330805450@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Date: Tue, 13 Feb 2024 22:04:00 +0100 (CET) From: Thomas Gleixner Provide a few helper functions to read CPUID leafs or individual registers into a data structure without requiring unions. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Tested-by: Sohil Mehta Tested-by: Michael Kelley Tested-by: Peter Zijlstra (Intel) Tested-by: Zhang Rui Tested-by: Wang Wendy Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/cpuid.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) --- --- a/arch/x86/include/asm/cpuid.h +++ b/arch/x86/include/asm/cpuid.h @@ -127,6 +127,42 @@ static inline unsigned int cpuid_edx(uns return edx; } +static inline void __cpuid_read(unsigned int leaf, unsigned int subleaf, u32 *regs) +{ + regs[CPUID_EAX] = leaf; + regs[CPUID_ECX] = subleaf; + __cpuid(regs, regs + 1, regs + 2, regs + 3); +} + +#define cpuid_subleaf(leaf, subleaf, regs) { \ + BUILD_BUG_ON(sizeof(*(regs)) != 16); \ + __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ +} + +#define cpuid_leaf(leaf, regs) { \ + BUILD_BUG_ON(sizeof(*(regs)) != 16); \ + __cpuid_read(leaf, 0, (u32 *)(regs)); \ +} + +static inline void __cpuid_read_reg(unsigned int leaf, unsigned int subleaf, + enum cpuid_regs_idx regidx, u32 *reg) +{ + u32 regs[4]; + + __cpuid_read(leaf, subleaf, regs); + *reg = regs[regidx]; +} + +#define cpuid_subleaf_reg(leaf, subleaf, regidx, reg) { \ + BUILD_BUG_ON(sizeof(*(reg)) != 4); \ + __cpuid_read_reg(leaf, subleaf, regidx, (u32 *)(reg)); \ +} + +#define cpuid_leaf_reg(leaf, regidx, reg) { \ + BUILD_BUG_ON(sizeof(*(reg)) != 4); \ + __cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg)); \ +} + static __always_inline bool cpuid_function_is_indexed(u32 function) { switch (function) {