From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH 1/2] arm64/sve: Ensure that all fields in ZCR_EL1 are set to known values
Date: Tue, 13 Feb 2024 15:32:45 +0000 [thread overview]
Message-ID: <20240213-arm64-fp-init-vec-cr-v1-1-7e7c2d584f26@kernel.org> (raw)
In-Reply-To: <20240213-arm64-fp-init-vec-cr-v1-0-7e7c2d584f26@kernel.org>
At present nothing in our CPU initialisation code ever sets unknown fields
in ZCR_EL1 to known values, all updates to ZCR_EL1 are read/modify/write
sequences for LEN. All the unknown fields are RES0, explicitly initialise
them as such to avoid future surprises.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/kernel/fpsimd.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index a5dc6f764195..cc3c9ad877a8 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -1134,6 +1134,8 @@ void cpu_enable_sve(const struct arm64_cpu_capabilities *__always_unused p)
{
write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1);
isb();
+
+ write_sysreg_s(0, SYS_ZCR_EL1);
}
void __init sve_setup(void)
--
2.30.2
next prev parent reply other threads:[~2024-02-13 15:35 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 15:32 [PATCH 0/2] arm64/fp: Initialise all bits in vector control registers " Mark Brown
2024-02-13 15:32 ` Mark Brown [this message]
2024-02-13 15:32 ` [PATCH 2/2] arm64/sme: Ensure that all fields in SMCR_EL1 are set " Mark Brown
2024-02-22 22:04 ` [PATCH 0/2] arm64/fp: Initialise all bits in vector control registers " Catalin Marinas
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