[PATCH -fixes v3 0/2] riscv: cbo.zero fixes

[Samuel Holland <samuel.holland@sifive.com>]

This series fixes a couple of issues related to using the cbo.zero
instruction in userspace. The first patch fixes a bug where the wrong
enable bit gets set if the kernel is running in M-mode. The second
patch fixes a bug where the enable bit gets reset to its default value
after a nonretentive idle state. I have hardware which reproduces this:

Before this series (or without ss1p12 in the devicetree):
  $ tools/testing/selftests/riscv/hwprobe/cbo
  TAP version 13
  1..3
  ok 1 Zicboz block size
  # Zicboz block size: 64
  Illegal instruction

After applying this series:
  $ tools/testing/selftests/riscv/hwprobe/cbo
  TAP version 13
  1..3
  ok 1 Zicboz block size
  # Zicboz block size: 64
  ok 2 cbo.zero
  ok 3 cbo.zero check
  # Totals: pass:3 fail:0 xfail:0 xpass:0 skip:0 error:0

Changes in v3:
 - Drop patches added in v2
 - Check for Zicboz instead of the privileged ISA version

Changes in v2:
 - Add patches to allow parsing the privileged ISA version from the DT
 - Check for privileged ISA v1.12 instead of the specific CSR
 - Use riscv_has_extension_likely() instead of new ALTERNATIVE()s

Samuel Holland (2):
  riscv: Fix enabling cbo.zero when running in M-mode
  riscv: Save/restore envcfg CSR during CPU suspend

 arch/riscv/include/asm/csr.h     | 2 ++
 arch/riscv/include/asm/suspend.h | 1 +
 arch/riscv/kernel/cpufeature.c   | 2 +-
 arch/riscv/kernel/suspend.c      | 4 ++++
 4 files changed, 8 insertions(+), 1 deletion(-)

-- 
2.43.0