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From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: "Marc Zyngier" <maz@kernel.org>, "Björn Töpel" <bjorn@kernel.org>,
	"Atish Patra" <atishp@atishpatra.org>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Sunil V L" <sunilvl@ventanamicro.com>,
	"Saravana Kannan" <saravanak@google.com>,
	"Anup Patel" <anup@brainfault.org>,
	linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	"Anup Patel" <apatel@ventanamicro.com>
Subject: [PATCH v13 02/13] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore
Date: Tue, 20 Feb 2024 11:37:07 +0530	[thread overview]
Message-ID: <20240220060718.823229-3-apatel@ventanamicro.com> (raw)
In-Reply-To: <20240220060718.823229-1-apatel@ventanamicro.com>

Now that PLIC driver is probed as a regular platform driver, the lock
dependency validator complains about the safety of handler->enable_lock
usage:

[    0.956775]  Possible interrupt unsafe locking scenario:

[    0.956998]        CPU0                    CPU1
[    0.957247]        ----                    ----
[    0.957439]   lock(&handler->enable_lock);
[    0.957607]                                local_irq_disable();
[    0.957793]                                lock(&irq_desc_lock_class);
[    0.958021]                                lock(&handler->enable_lock);
[    0.958246]   <Interrupt>
[    0.958342]     lock(&irq_desc_lock_class);
[    0.958501]
                *** DEADLOCK ***

To address above, let's use raw_spin_lock_irqsave/unlock_irqrestore()
instead of raw_spin_lock/unlock().

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/irqchip/irq-sifive-plic.c | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 48483a1a41dd..e91077ff171f 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -103,9 +103,11 @@ static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
 
 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
 {
-	raw_spin_lock(&handler->enable_lock);
+	unsigned long flags;
+
+	raw_spin_lock_irqsave(&handler->enable_lock, flags);
 	__plic_toggle(handler->enable_base, hwirq, enable);
-	raw_spin_unlock(&handler->enable_lock);
+	raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
 }
 
 static inline void plic_irq_toggle(const struct cpumask *mask,
@@ -236,6 +238,7 @@ static int plic_irq_set_type(struct irq_data *d, unsigned int type)
 static int plic_irq_suspend(void)
 {
 	unsigned int i, cpu;
+	unsigned long flags;
 	u32 __iomem *reg;
 	struct plic_priv *priv;
 
@@ -253,12 +256,12 @@ static int plic_irq_suspend(void)
 		if (!handler->present)
 			continue;
 
-		raw_spin_lock(&handler->enable_lock);
+		raw_spin_lock_irqsave(&handler->enable_lock, flags);
 		for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
 			reg = handler->enable_base + i * sizeof(u32);
 			handler->enable_save[i] = readl(reg);
 		}
-		raw_spin_unlock(&handler->enable_lock);
+		raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
 	}
 
 	return 0;
@@ -267,6 +270,7 @@ static int plic_irq_suspend(void)
 static void plic_irq_resume(void)
 {
 	unsigned int i, index, cpu;
+	unsigned long flags;
 	u32 __iomem *reg;
 	struct plic_priv *priv;
 
@@ -284,12 +288,12 @@ static void plic_irq_resume(void)
 		if (!handler->present)
 			continue;
 
-		raw_spin_lock(&handler->enable_lock);
+		raw_spin_lock_irqsave(&handler->enable_lock, flags);
 		for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) {
 			reg = handler->enable_base + i * sizeof(u32);
 			writel(handler->enable_save[i], reg);
 		}
-		raw_spin_unlock(&handler->enable_lock);
+		raw_spin_unlock_irqrestore(&handler->enable_lock, flags);
 	}
 }
 
-- 
2.34.1


  parent reply	other threads:[~2024-02-20  6:07 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-20  6:07 [PATCH v13 00/13] Linux RISC-V AIA Support Anup Patel
2024-02-20  6:07 ` [PATCH v13 01/13] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-02-20 10:09   ` Thomas Gleixner
2024-02-22  9:25     ` Anup Patel
2024-02-20  6:07 ` Anup Patel [this message]
2024-02-20 10:11   ` [PATCH v13 02/13] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore Thomas Gleixner
2024-02-21 13:35     ` Anup Patel
2024-02-20  6:07 ` [PATCH v13 03/13] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-02-20 10:13   ` Thomas Gleixner
2024-02-21 13:32     ` Anup Patel
2024-02-20  6:07 ` [PATCH v13 04/13] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-02-20  6:07 ` [PATCH v13 05/13] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-02-20  6:07 ` [PATCH v13 06/13] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-20 11:52   ` Björn Töpel
2024-02-20 13:00     ` Anup Patel
2024-02-21 11:59       ` Björn Töpel
2024-02-21 12:23         ` Anup Patel
2024-02-21 17:22           ` Björn Töpel
2024-02-20 11:53   ` Björn Töpel
2024-02-20 13:15     ` Anup Patel
2024-02-20 13:15   ` Thomas Gleixner
2024-02-20 16:33     ` Anup Patel
2024-02-20  6:07 ` [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-20 11:53   ` Björn Töpel
2024-02-20 16:39     ` Anup Patel
2024-02-20 13:32   ` Thomas Gleixner
2024-02-20 16:52     ` Anup Patel
2024-02-20 17:12       ` Thomas Gleixner
2024-02-20  6:07 ` [PATCH v13 08/13] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-20 13:35   ` Thomas Gleixner
2024-02-20 17:21     ` Anup Patel
2024-02-20 20:03       ` Thomas Gleixner
2024-02-20  6:07 ` [PATCH v13 09/13] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-02-20  6:07 ` [PATCH v13 10/13] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-20 13:40   ` Thomas Gleixner
2024-02-21  5:42     ` Anup Patel
2024-02-20  6:07 ` [PATCH v13 11/13] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-20  6:07 ` [PATCH v13 12/13] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-02-20  6:07 ` [PATCH v13 13/13] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
2024-02-20 11:52 ` [PATCH v13 00/13] Linux RISC-V AIA Support Björn Töpel
2024-02-20 13:09   ` Anup Patel

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