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X-CSE-ConnectionGUID: M/vfrS4FS22yqV9NCgJOCw== X-CSE-MsgGUID: AaMFphW2QQqFpaO8uyVc3g== X-IronPort-AV: E=Sophos;i="6.06,195,1705388400"; d="asc'?scan'208";a="18671665" X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 01 Mar 2024 02:32:06 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 1 Mar 2024 02:31:49 -0700 Received: from wendy (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Fri, 1 Mar 2024 02:31:47 -0700 Date: Fri, 1 Mar 2024 09:31:04 +0000 From: Conor Dooley To: Samuel Holland CC: Palmer Dabbelt , , , , Alexandre Ghiti , Jisheng Zhang , Yunhui Cui Subject: Re: [PATCH v5 00/13] riscv: ASID-related and UP-related TLB flush enhancements Message-ID: <20240301-dreadful-discourse-6f1bb453d9c6@wendy> References: <20240229232211.161961-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="KuBrCPUMUGSkl7W1" Content-Disposition: inline In-Reply-To: <20240229232211.161961-1-samuel.holland@sifive.com> --KuBrCPUMUGSkl7W1 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Feb 29, 2024 at 03:21:41PM -0800, Samuel Holland wrote: > Samuel Holland (13): > riscv: Flush the instruction cache during SMP bringup > riscv: Factor out page table TLB synchronization =46rom here onwards, fails on 32-bit, bunch of implicit-function-declaration stuff. > riscv: Use IPIs for remote cache/TLB flushes by default > riscv: mm: Broadcast kernel TLB flushes only when needed > riscv: Only send remote fences when some other CPU is online > riscv: mm: Combine the SMP and UP TLB flush code > riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma > riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 > riscv: mm: Introduce cntx2asid/cntx2version helper macros > riscv: mm: Use a fixed layout for the MM context ID > riscv: mm: Make asid_bits a local variable > riscv: mm: Preserve global TLB entries when switching contexts > riscv: mm: Always use an ASID to flush mm contexts --KuBrCPUMUGSkl7W1 Content-Type: application/pgp-signature; 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