[PATCH] arm64: dts: r9a07g044: Add complete CPU cache information

[Tim Pambor <tp@osasysteme.de>]

Based on ARM Cortex-A55 TRM and RZG2/L user's manual, each Cortex-A55 has
- 32 KB of L1 4-way, set-associative instruction cache
- 32 KB of L1 4-way, set-associative data cache

Each cache has a cache line length of 64B and therefore there are
32768B/(4 * 64B)=128 sets for each cache.

RZG2/L are not configured with the optional per-core L2 cache but only
have a L3 cache shared among all cores. In this case, the L3 cache appears
as a L2 cache to the system. Therefore, specify "cache-level = <2>" for
the L3 cache.

Signed-off-by: Tim Pambor <tp@osasysteme.de>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 9f00b75d2bd0..6379c850526a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -89,6 +89,12 @@ cpu0: cpu@0 {
 			reg = <0>;
 			device_type = "cpu";
 			#cooling-cells = <2>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
@@ -99,6 +105,12 @@ cpu1: cpu@100 {
 			compatible = "arm,cortex-a55";
 			reg = <0x100>;
 			device_type = "cpu";
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <128>;
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
@@ -109,7 +121,7 @@ L3_CA55: cache-controller-0 {
 			compatible = "cache";
 			cache-unified;
 			cache-size = <0x40000>;
-			cache-level = <3>;
+			cache-level = <2>;
 		};
 	};
 
-- 
2.43.0