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AJvYcCUyzl+6QjqdJrvtXRZZG13VRuA5VKhL8DDha67CjiosKa7Qj9BvS0SYM8gEj2zSgAZ05w4q4KH/bCc080npUAMQAhtsBpBJgfPjCtOS X-Gm-Message-State: AOJu0YwETTh7ZlbRn5uaW262wN9zOs32MEYeT3UX43XIJ8CumQJr28Sh 3kmROVhWkGl1yUYOSlqqhTpMHvkzYqDm/Oe04PknMk9e1mdHK65xu1zoarq8Kcg= X-Google-Smtp-Source: AGHT+IFC7Ostz4NVqRl+TdyivWIDYqcK3ZnTae/PQDs3xYi5nfAgFK24gkFZANSYBnnATXXDHJF4Cw== X-Received: by 2002:a17:90b:80a:b0:2a5:513:921e with SMTP id bk10-20020a17090b080a00b002a50513921emr5443131pjb.31.1713063584355; Sat, 13 Apr 2024 19:59:44 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.246]) by smtp.gmail.com with ESMTPSA id cx15-20020a17090afd8f00b002a219f8079fsm4799913pjb.33.2024.04.13.19.59.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sat, 13 Apr 2024 19:59:43 -0700 (PDT) From: Yunhui Cui To: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, sudeep.holla@arm.com, tiantao6@huawei.com Cc: Yunhui Cui Subject: [PATCH v2 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT Date: Sun, 14 Apr 2024 10:58:25 +0800 Message-Id: <20240414025826.64025-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20240414025826.64025-1-cuiyunhui@bytedance.com> References: <20240414025826.64025-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Before cacheinfo can be built correctly, we need to initialize level and type. Since RSIC-V currently does not have a register group that describes cache-related attributes like ARM64, we cannot obtain them directly, so now we obtain cache leaves from the ACPI PPTT table (acpi_get_cache_info()) and set the cache type through split_levels. Suggested-by: Jeremy Linton Suggested-by: Sudeep Holla Signed-off-by: Yunhui Cui --- arch/riscv/kernel/cacheinfo.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 30a6878287ad..ece92aa404e3 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -6,6 +6,7 @@ #include #include #include +#include static struct riscv_cacheinfo_ops *rv_cache_ops; @@ -78,6 +79,28 @@ int populate_cache_leaves(unsigned int cpu) struct device_node *prev = NULL; int levels = 1, level = 1; + if (!acpi_disabled) { + int ret, idx, fw_levels, split_levels; + + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); + if (ret) + return ret; + + /* must be set, so we can drop num_leaves assignment below */ + this_cpu_ci->num_leaves = fw_levels + split_levels; + + for (idx = 0; level <= this_cpu_ci->num_levels && + idx < this_cpu_ci->num_leaves; idx++, level++) { + if (level <= split_levels) { + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); + } else { + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); + } + } + return 0; + } + if (of_property_read_bool(np, "cache-size")) ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); if (of_property_read_bool(np, "i-cache-size")) -- 2.20.1