From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8CCE31E489; Thu, 18 Apr 2024 08:41:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713429713; cv=none; b=ccchZWRrUA0M3fqT+F1Px8DWd9jDFtqygGG/zH6XwLKJZmp+WWf7AZf7idARtRSlXpng2L7NKZ1ADaPn5wKmgYX0LXo+iRVSpxxUHrfCS65t7EufgyzKlugPTQyBb/ggusGbODm4zWjqcQjUEss7VWRMJMTJ6a9d8VKJkQzswMM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713429713; c=relaxed/simple; bh=URxXzo454+UtOJFZjWtTQ85nOYvNyQvS+Up9pA1mQxA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=APSn1shogWav7VTUeVOQZ1eeI5kAd3V2SFVsnLhBuk0vZdvZCG/vch8XMgxnX06AH+U/5+XrmOHwhYMClZNDZVmx2Gwj3iX3Sa4CGLvvfNpYXGvSmnEAyemT9w9mS8vxaPdYIA6AQJkjutrGAOa2pivGhEY8ekIjsSDMWbWqe64= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 35794339; Thu, 18 Apr 2024 01:42:17 -0700 (PDT) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0E4B3F64C; Thu, 18 Apr 2024 01:41:46 -0700 (PDT) Date: Thu, 18 Apr 2024 09:41:44 +0100 From: Sudeep Holla To: Yunhui Cui Cc: rafael@kernel.org, lenb@kernel.org, linux-acpi@vger.kernel.org, Sudeep Holla , linux-kernel@vger.kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org, bhelgaas@google.com, james.morse@arm.com, jhugo@codeaurora.org, jeremy.linton@arm.com, john.garry@huawei.com, Jonathan.Cameron@huawei.com, pierre.gondois@arm.com, tiantao6@huawei.com Subject: Re: [PATCH v4 2/3] riscv: cacheinfo: initialize cacheinfo's level and type from ACPI PPTT Message-ID: <20240418084144.go3zk5yycsg6e2k2@bogus> References: <20240418034330.84721-1-cuiyunhui@bytedance.com> <20240418034330.84721-2-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240418034330.84721-2-cuiyunhui@bytedance.com> On Thu, Apr 18, 2024 at 11:43:29AM +0800, Yunhui Cui wrote: > Before cacheinfo can be built correctly, we need to initialize level > and type. Since RSIC-V currently does not have a register group that > describes cache-related attributes like ARM64, we cannot obtain them > directly, so now we obtain cache leaves from the ACPI PPTT table > (acpi_get_cache_info()) and set the cache type through split_levels. > > Suggested-by: Jeremy Linton > Suggested-by: Sudeep Holla > Signed-off-by: Yunhui Cui > --- > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c > index 30a6878287ad..e47a1e6bd3fe 100644 > --- a/arch/riscv/kernel/cacheinfo.c > +++ b/arch/riscv/kernel/cacheinfo.c > @@ -6,6 +6,7 @@ > #include > #include > #include > +#include > > static struct riscv_cacheinfo_ops *rv_cache_ops; > > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu) > struct device_node *prev = NULL; > int levels = 1, level = 1; > > + if (!acpi_disabled) { > + int ret, fw_levels, split_levels; > + > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); > + if (ret) > + return ret; > + > + BUG_ON((split_levels > fw_levels) || > + (split_levels + fw_levels > this_cpu_ci->num_leaves)); > + > + for (; level <= this_cpu_ci->num_levels; level++) { > + if (level <= split_levels) { > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); > + } else { > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); > + } > + } > + return 0; > + } > + Much better, so my review still stands 😄 Reviewed-by: Sudeep Holla > if (of_property_read_bool(np, "cache-size")) > ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); > if (of_property_read_bool(np, "i-cache-size")) > -- > 2.20.1 > -- Regards, Sudeep