From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 71C6416F90A for ; Fri, 26 Apr 2024 15:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714144219; cv=none; b=Q9jhE68NRTLWhDX6nkcn36gFuX/vAunbeZe4ywAIS8G9eSxpaCLJv6AG0A8w2Uy5/Fy5N3ShzdCFf6tBYhJi26fk+6dJ/gNiXvliIzOIOi3MPZCsEk9Z2CJDpl2xQzG6FN/k9BMkzmPQwvddSTIkjrRlQRjfXvC9odZ7W8bzGME= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714144219; c=relaxed/simple; bh=PAli0NZM95hR3J7V5Sv3ooc3cjADYmquhPjDYGYrnRI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nW36+FfmYM1Ftx8DB3/9VoIulUnVulNOHpvJXLFrl2FCq+YV7cSsaM3VajAXqJT9hB08Cn2pVCPX6uZM62Av0RGUYhjwebXWuYf+w4uQbUFIBdr9rY65aMAZhVy/LobdS3D8u2j8X6iZYTUPtiZcWwC+Qde0RFP49pORN2M8uX4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E6E5D1007; Fri, 26 Apr 2024 08:10:45 -0700 (PDT) Received: from e133380.cambridge.arm.com (e133380.arm.com [10.1.197.52]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0DE953F73F; Fri, 26 Apr 2024 08:10:14 -0700 (PDT) From: Dave Martin To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: James Morse , Fenghua Yu , Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Babu Moger , shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, "Shaopeng Tan (Fujitsu)" , baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , Peter Newman , dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Rex Nie Subject: [PATCH v2 21/35] x86/resctrl: Make prefetch_disable_bits belong to the arch code Date: Fri, 26 Apr 2024 16:08:50 +0100 Message-Id: <20240426150904.8854-21-Dave.Martin@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240426150904.8854-1-Dave.Martin@arm.com> References: <20240426150537.8094-1-Dave.Martin@arm.com> <20240426150904.8854-1-Dave.Martin@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: James Morse prefetch_disable_bits is set by rdtgroup_locksetup_enter() from a value provided by the architecture, but is largely read by other architecture helpers. Instead of exporting this value, make resctrl_arch_get_prefetch_disable_bits() set it so that the other arch-code helpers can use the cached-value. Signed-off-by: James Morse --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 856beb6f668b..5a66e3b2c2ea 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -85,6 +85,8 @@ static const struct class pseudo_lock_class = { */ u64 resctrl_arch_get_prefetch_disable_bits(void) { + prefetch_disable_bits = 0; + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || boot_cpu_data.x86 != 6) return 0; @@ -100,7 +102,8 @@ u64 resctrl_arch_get_prefetch_disable_bits(void) * 3 DCU IP Prefetcher Disable (R/W) * 63:4 Reserved */ - return 0xF; + prefetch_disable_bits = 0xF; + break; case INTEL_FAM6_ATOM_GOLDMONT: case INTEL_FAM6_ATOM_GOLDMONT_PLUS: /* @@ -111,10 +114,11 @@ u64 resctrl_arch_get_prefetch_disable_bits(void) * 2 DCU Hardware Prefetcher Disable (R/W) * 63:3 Reserved */ - return 0x5; + prefetch_disable_bits = 0x5; + break; } - return 0; + return prefetch_disable_bits; } /** @@ -715,8 +719,7 @@ int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp) * Not knowing the bits to disable prefetching implies that this * platform does not support Cache Pseudo-Locking. */ - prefetch_disable_bits = resctrl_arch_get_prefetch_disable_bits(); - if (prefetch_disable_bits == 0) { + if (resctrl_arch_get_prefetch_disable_bits() == 0) { rdt_last_cmd_puts("Pseudo-locking not supported\n"); return -EINVAL; } -- 2.34.1