From: Florian Fainelli <florian.fainelli@broadcom.com>
To: linux-arm-kernel@lists.infradead.org
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
"Hauke Mehrtens" <hauke@hauke-m.de>,
"Rafał Miłecki" <zajec5@gmail.com>,
"Broadcom internal kernel review list"
<bcm-kernel-feedback-list@broadcom.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Conor Dooley" <conor+dt@kernel.org>,
devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND
FLATTENED DEVICE TREE BINDINGS),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 1/2] ARM: dts: BCM5301X: Relocate PCIe nodes to top-level
Date: Tue, 30 Apr 2024 16:07:13 -0700 [thread overview]
Message-ID: <20240430230714.3923578-2-florian.fainelli@broadcom.com> (raw)
In-Reply-To: <20240430230714.3923578-1-florian.fainelli@broadcom.com>
In order to have the PCIe node(s) gain a "ranges" property which is
meaningful, move them out of the axi@18000000 bus node towards the
top-level.
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
arch/arm/boot/dts/broadcom/bcm-ns.dtsi | 79 +++++++++++++-------------
1 file changed, 40 insertions(+), 39 deletions(-)
diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
index d0d5f7e52a91..8f69da8d18c2 100644
--- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi
@@ -121,28 +121,28 @@ axi@18000000 {
<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
/* PCIe Controller 0 */
- <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
- <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
- <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
- <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
- <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
- <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
/* PCIe Controller 1 */
- <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
- <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
- <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
- <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
- <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
/* PCIe Controller 2 */
- <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
- <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
- <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
- <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
- <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <0x18014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
/* USB 2.0 Controller */
<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
@@ -181,27 +181,6 @@ chipcommon: chipcommon@0 {
#interrupt-cells = <2>;
};
- pcie0: pcie@12000 {
- reg = <0x00012000 0x1000>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- };
-
- pcie1: pcie@13000 {
- reg = <0x00013000 0x1000>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- };
-
- pcie2: pcie@14000 {
- reg = <0x00014000 0x1000>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- };
-
usb2: usb2@21000 {
reg = <0x00021000 0x1000>;
@@ -494,6 +473,28 @@ usb3_dmp: syscon@18105000 {
reg = <0x18105000 0x1000>;
};
+ pcie0: pcie@18012000 {
+ reg = <0x18012000 0x1000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ };
+
+ pcie1: pcie@18013000 {
+ reg = <0x18013000 0x1000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ };
+
+ pcie2: pcie@18014000 {
+ reg = <0x18014000 0x1000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ };
+
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
--
2.34.1
next prev parent reply other threads:[~2024-04-30 23:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 23:07 [PATCH 0/2] ARM: dts: BCM5301X: Fix PCIe controller warnings Florian Fainelli
2024-04-30 23:07 ` Florian Fainelli [this message]
2024-04-30 23:07 ` [PATCH 2/2] ARM: dts: BCM5301X: Describe PCIe controllers fully Florian Fainelli
2024-05-31 21:33 ` [PATCH 0/2] ARM: dts: BCM5301X: Fix PCIe controller warnings Florian Fainelli
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