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[98.197.58.203]) by smtp.gmail.com with ESMTPSA id w2-20020a056808018200b003c8643f0e5csm1067872oic.16.2024.04.30.21.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 21:08:01 -0700 (PDT) From: Alexandru Gagniuc To: Cc: linux-kernel@vger.kernel.org, quic_kathirav@quicinc.com, Alexandru Gagniuc Subject: [PATCH v4 0/8] ipq9574: Enable PCI-Express support Date: Tue, 30 Apr 2024 23:07:42 -0500 Message-Id: <20240501040800.1542805-1-mr.nuke.me@gmail.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit There are four PCIe ports on IPQ9574, pcie0 thru pcie3. This series addresses pcie2, which is a gen3x2 port. The board I have only uses pcie2, and that's the only one enabled in this series. pcie3 is added as a special request, but is untested. I believe this makes sense as a monolithic series, as the individual pieces are not that useful by themselves. In v2, I've had some issues regarding the dt schema checks. For transparency, I used the following test invocations to test: make dt_binding_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml make dtbs_check DT_SCHEMA_FILES=qcom,pcie.yaml:qcom,ipq8074-qmp-pcie-phy.yaml Changes since v3: - "const"ify .hw.init fields for the PCIE pipe clocks - Used pciephy_v5_regs_layout instead of v4 in phy-qcom-qmp-pcie.c - Included Manivannan's patch for qcom-pcie.c clocks - Dropped redundant comments in "ranges" and "interrupt-map" of pcie2. - Added pcie3 and pcie3_phy dts nodes - Moved snoc and anoc clocks to PCIe controller from PHY Changes since v2: - reworked resets in qcom,pcie.yaml to resolve dt schema errors - constrained "reg" in qcom,pcie.yaml - reworked min/max intems in qcom,ipq8074-qmp-pcie-phy.yaml - dropped msi-parent for pcie node, as it is handled by "msi" IRQ Changes since v1: - updated new tables in phy-qcom-qmp-pcie.c to use lowercase hex numbers - reorganized qcom,ipq8074-qmp-pcie-phy.yaml to use a single list of clocks - reorganized qcom,pcie.yaml to include clocks+resets per compatible - Renamed "pcie2_qmp_phy" label to "pcie2_phy" - moved "ranges" property of pcie@20000000 higher up Alexandru Gagniuc (7): dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 clk: qcom: gcc-ipq9574: Add PCIe pipe clocks dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller PCI: qcom: Add support for IPQ9574 dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY arm64: dts: qcom: ipq9574: add PCIe2 nodes Alexandru Gagniuc (7): dt-bindings: clock: Add PCIe pipe related clocks for IPQ9574 clk: qcom: gcc-ipq9574: Add PCIe pipe clocks dt-bindings: PCI: qcom: Add IPQ9574 PCIe controller PCI: qcom: Add support for IPQ9574 dt-bindings: phy: qcom,ipq8074-qmp-pcie: add ipq9574 gen3x2 PHY phy: qcom-qmp-pcie: add support for ipq9574 gen3x2 PHY arm64: dts: qcom: ipq9574: add PCIe2 and PCIe3 nodes Manivannan Sadhasivam (1): PCI: qcom: Switch to devm_clk_bulk_get_all() API to get the clocks from Devicetree .../devicetree/bindings/pci/qcom,pcie.yaml | 37 ++++ .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 1 + arch/arm64/boot/dts/qcom/ipq9574.dtsi | 178 +++++++++++++++++- drivers/clk/qcom/gcc-ipq9574.c | 76 ++++++++ drivers/pci/controller/dwc/pcie-qcom.c | 164 +++------------- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 136 ++++++++++++- .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 14 ++ include/dt-bindings/clock/qcom,ipq9574-gcc.h | 4 + 8 files changed, 469 insertions(+), 141 deletions(-) -- 2.40.1