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From: Jason Gunthorpe <jgg@ziepe.ca>
To: Zong Li <zong.li@sifive.com>
Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
	tjeznach@rivosinc.com, paul.walmsley@sifive.com,
	palmer@dabbelt.com, aou@eecs.berkeley.edu, kevin.tian@intel.com,
	linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH RFC RESEND 3/6] iommu/riscv: support GSCID
Date: Tue, 7 May 2024 12:15:16 -0300	[thread overview]
Message-ID: <20240507151516.GK901876@ziepe.ca> (raw)
In-Reply-To: <20240507142600.23844-4-zong.li@sifive.com>

On Tue, May 07, 2024 at 10:25:57PM +0800, Zong Li wrote:
> @@ -919,29 +924,43 @@ static void riscv_iommu_iotlb_inval(struct riscv_iommu_domain *domain,
>  	rcu_read_lock();
>  
>  	prev = NULL;
> -	list_for_each_entry_rcu(bond, &domain->bonds, list) {
> -		iommu = dev_to_iommu(bond->dev);
>  
> -		/*
> -		 * IOTLB invalidation request can be safely omitted if already sent
> -		 * to the IOMMU for the same PSCID, and with domain->bonds list
> -		 * arranged based on the device's IOMMU, it's sufficient to check
> -		 * last device the invalidation was sent to.
> -		 */
> -		if (iommu == prev)
> -			continue;
> -
> -		riscv_iommu_cmd_inval_vma(&cmd);
> -		riscv_iommu_cmd_inval_set_pscid(&cmd, domain->pscid);
> -		if (len && len >= RISCV_IOMMU_IOTLB_INVAL_LIMIT) {
> -			for (iova = start; iova < end; iova += PAGE_SIZE) {
> -				riscv_iommu_cmd_inval_set_addr(&cmd, iova);
> +	/*
> +	 * Host domain needs to flush entries in stage-2 for MSI mapping.
> +	 * However, device is bound to s1 domain instead of s2 domain.
> +	 * We need to flush mapping without looping devices of s2 domain
> +	 */
> +	if (domain->gscid) {
> +		riscv_iommu_cmd_inval_gvma(&cmd);
> +		riscv_iommu_cmd_inval_set_gscid(&cmd, domain->gscid);
> +		riscv_iommu_cmd_send(iommu, &cmd, 0);
> +		riscv_iommu_cmd_iofence(&cmd);
> +		riscv_iommu_cmd_send(iommu, &cmd, RISCV_IOMMU_QUEUE_TIMEOUT);

Is iommu null here? Where did it come from?

This looks wrong too. The "bonds" list is sort of misnamed, it is
really a list of invalidation instructions. If you need a special
invalidation instruction for this case then you should allocate a
memory and add it to the bond list when the attach is done.

Invalidation should simply iterate over the bond list and do the
instructions it contains, always.

>  static void riscv_iommu_iodir_update(struct riscv_iommu_device *iommu,
> -				     struct device *dev, u64 fsc, u64 ta)
> +				     struct device *dev, u64 fsc, u64 ta, u64 iohgatp)

I think you should make a struct to represent the dc entry.

Jason

  reply	other threads:[~2024-05-07 15:15 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-07 14:25 [PATCH RFC RESEND 0/6] RISC-V IOMMU HPM and nested IOMMU support Zong Li
2024-05-07 14:25 ` [PATCH RFC RESEND 1/6] iommu/riscv: Add RISC-V IOMMU PMU support Zong Li
2024-05-07 14:25 ` [PATCH RFC RESEND 2/6] iommu/riscv: Support HPM and interrupt handling Zong Li
2024-05-07 14:25 ` [PATCH RFC RESEND 3/6] iommu/riscv: support GSCID Zong Li
2024-05-07 15:15   ` Jason Gunthorpe [this message]
2024-05-07 15:52     ` Zong Li
2024-05-07 16:25       ` Jason Gunthorpe
2024-05-07 14:25 ` [PATCH RFC RESEND 4/6] iommu/riscv: support nested iommu for getting iommu hardware information Zong Li
2024-05-07 14:54   ` Jason Gunthorpe
2024-05-07 15:19     ` Zong Li
2024-05-07 14:25 ` [PATCH RFC RESEND 5/6] iommu/riscv: support nested iommu for creating domains owned by userspace Zong Li
2024-05-07 15:07   ` Jason Gunthorpe
2024-05-07 14:26 ` [PATCH RFC RESEND 6/6] iommu/riscv: support nested iommu for flushing cache Zong Li
2024-05-07 15:08   ` Jason Gunthorpe
2024-05-07 15:35     ` Zong Li
2024-05-07 16:27       ` Jason Gunthorpe

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