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[93.34.90.105]) by smtp.googlemail.com with ESMTPSA id fk12-20020a05600c0ccc00b0041c130520fbsm2921555wmb.46.2024.05.08.10.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:07:39 -0700 (PDT) From: Christian Marangi To: Hauke Mehrtens , =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Christian Marangi , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property Date: Wed, 8 May 2024 19:07:18 +0200 Message-ID: <20240508170721.3023-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240508170721.3023-1-ansuelsmth@gmail.com> References: <20240508170721.3023-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0 if called from TP1. The CBR address is always the same on the SoC hence it can be provided in DT to handle broken case where bootloader doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by: Christian Marangi --- .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml index 975945ca2888..77f73ab48c11 100644 --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml @@ -55,6 +55,15 @@ properties: under the "cpus" node. $ref: /schemas/types.yaml#/definitions/uint32 + brcm,bmips-cbr-reg: + description: Reference address of the CBR. + Some SoC suffer from a BUG where read_c0_brcm_cbr() might + return 0 if called from TP1. The CBR address is always the + same on the SoC hence it can be provided in DT to handle + broken case where bootloader doesn't initialise it or SMP + where read_c0_brcm_cbr() returns 0 from TP1. + $ref: /schemas/types.yaml#/definitions/uint32 + patternProperties: "^cpu@[0-9]$": type: object @@ -64,6 +73,20 @@ properties: required: - mips-hpt-frequency +if: + properties: + compatible: + contains: + enum: + - brcm,bcm6358 + - brcm,bcm6368 + +then: + properties: + cpus: + required: + - brcm,bmips-cbr-reg + additionalProperties: true examples: -- 2.43.0