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Wed, 22 May 2024 11:22:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG5vZvG6tsDWXDP5VEip3wRFTIGOmtPrEdCqdECt3XJLP2LbA45K02hd5EjKoficyR2hUPYOg== X-Received: by 2002:a05:6808:241:b0:3c9:c755:a194 with SMTP id 5614622812f47-3cdbc568b62mr2526898b6e.59.1716402160051; Wed, 22 May 2024 11:22:40 -0700 (PDT) Received: from redhat.com ([38.15.36.11]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3c99308f4f3sm4570470b6e.13.2024.05.22.11.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 May 2024 11:22:39 -0700 (PDT) Date: Wed, 22 May 2024 12:22:37 -0600 From: Alex Williamson To: Jason Gunthorpe Cc: "Tian, Kevin" , "Vetter, Daniel" , "Zhao, Yan Y" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "x86@kernel.org" , "iommu@lists.linux.dev" , "pbonzini@redhat.com" , "seanjc@google.com" , "dave.hansen@linux.intel.com" , "luto@kernel.org" , "peterz@infradead.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "bp@alien8.de" , "hpa@zytor.com" , "corbet@lwn.net" , "joro@8bytes.org" , "will@kernel.org" , "robin.murphy@arm.com" , "baolu.lu@linux.intel.com" , "Liu, Yi L" Subject: Re: [PATCH 4/5] vfio/type1: Flush CPU caches on DMA pages in non-coherent domains Message-ID: <20240522122237.1b4bf782.alex.williamson@redhat.com> In-Reply-To: <20240522165221.GC20229@nvidia.com> References: <20240517171117.GB20229@nvidia.com> <20240521160714.GJ20229@nvidia.com> <20240521102123.7baaf85a.alex.williamson@redhat.com> <20240521163400.GK20229@nvidia.com> <20240521121945.7f144230.alex.williamson@redhat.com> <20240521183745.GP20229@nvidia.com> <20240522122939.GT20229@nvidia.com> <20240522084318.43e0dbb1.alex.williamson@redhat.com> <20240522165221.GC20229@nvidia.com> X-Mailer: Claws Mail 4.2.0 (GTK 3.24.41; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 22 May 2024 13:52:21 -0300 Jason Gunthorpe wrote: > On Wed, May 22, 2024 at 08:43:18AM -0600, Alex Williamson wrote: > > > But I think this also means that regardless of virtualizing > > PCI_EXP_DEVCTL_NOSNOOP_EN, there will be momentary gaps around device > > resets where a device could legitimately perform no-snoop > > transactions. > > Isn't memory enable turned off after FLR? If not do we have to make it > off before doing FLR? > > I'm not sure how a no-snoop could leak out around FLR? Good point, modulo s/memory/bus master/. Yes, we'd likely need to make sure we enter pci_reset_function() with BM disabled so that we don't have an ordering issue between restoring the PCIe capability and the command register. Likewise no-snoop handling would need to avoid gaps around backdoor resets like we try to do when we're masking INTx support on the device (vfio_bar_restore). Thanks, Alex