From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 977FD60DFA; Mon, 27 May 2024 08:42:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716799348; cv=none; b=uICRv1a46jv0vg3yIlxhJ8YLNfvlZtLdaLmnhYiR1SmEFp4BzPOWEQeOUg8dZRUJ/wQneq+SDPlOue4oS6pqCK0xkir/M+ApmvjiEgUDDMfTc+13ONrkmYh9K5QDQWXfq1O15DLNasGYVQ1MsNsBJtWSFsuTSs9QLjRHCP9WPcM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716799348; c=relaxed/simple; bh=hs++Omkr/DF0lEqyrohYJBJDmMi8MbjKZYJ3lcE1Jbk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R3+wKL0y5fMb0EqUCygaFhFPj/8nAcQm3ltrBRMRc5/4L0bNQyU7tC1KmI649wVKz6GmKAhSfoI+4t+LHzk/0elp2Ltlkypoe/eQ1Zb0+YVRphlUnKov2lvmDbtP9DS6ZamDFmQ8SBIQ5WFTAPMQAf2li3LhM/ZYsueH74BFhWY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=jgb+vn7z; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="jgb+vn7z" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44R5fcOS027334; Mon, 27 May 2024 01:42:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=E I31isaoru7lutdcciRfEyA1Qmp8HmW988aKddMR5wc=; b=jgb+vn7zRlt1/ecoT nCZnvjcs0sps8NFZaop8ktteNmh5OYbHGKE4inzBeGAERFRLJLc7ITSOJds891i8 Ss98kORkS4HmpAFVfOIn/6MI6vcKQmbvCkMvssCF0Mq+Hg6R0xte/5WLiRcDrolt zXancRWtJ/HkoEDpT9b8MpaJUkvwc0Dehz4+c2I6Kc7dUd9pj4X5bBxRAevwoazl 3TQrIaxx9M1x+os2tYpfvzLoSqMawn2Us4U5zJcpQ1tq1iJD7iKxLTgvbL4D+aE7 qtU1o6sgbY/Y0EKJIG4s02X5sUycSiI2OZweyrhKhktF++Wg9TLpay7fB4RyknEL uITYg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ycm8grk6p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 27 May 2024 01:42:22 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 27 May 2024 01:42:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 27 May 2024 01:42:21 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 602933F7062; Mon, 27 May 2024 01:42:21 -0700 (PDT) From: Witold Sadowski To: , , CC: , , , , , Witold Sadowski Subject: [PATCH v5 0/5] Marvell HW overlay support for Cadence xSPI Date: Mon, 27 May 2024 01:42:11 -0700 Message-ID: <20240527084216.667380-2-wsadowski@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240527084216.667380-1-wsadowski@marvell.com> References: <20240527084216.667380-1-wsadowski@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: IZUSsHYrozRXD2THjHiNHWcbV5WcZ6ee X-Proofpoint-ORIG-GUID: IZUSsHYrozRXD2THjHiNHWcbV5WcZ6ee X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-26_09,2024-05-24_01,2024-05-17_01 This patch series adds support for the second version of the Marvell hardware overlay for the Cadence xSPI IP block. The overlay is a hardware change made around the original xSPI block. It extends xSPI features with clock configuration, interrupt masking, and full-duplex, variable-length SPI operations. These functionalities allow the xSPI block to operate not only with memory devices but also with simple SPI devices and TPM devices. Changes: v5: Rework cdns,xspi.yaml file Reword commit messages Move mamory mapping to ACPI patch Use devm_platform_ioremap_resource instead of two step mapping v4: Rename new Marvell registers to keep naming conventions Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor Various fixed for cdns,xspi.yaml file: - Remove unnecesary parameters - Link register xferbase with marvell,cn10-xspi-nor - Move default values to .c file from device-tree Clock configuration optimization ACPI fixes: - Remove incorrect ACPI match table Added .data field to device_id, fixes for matching in ACPI and dtb case Minor style comment changes v3: Removed all kconfig changes Added device-tree mrvl,xspi-nor tag v2: Support for second overlay iteration v1: - v0: Initial support for v1 overlay Piyush Malgujar (1): spi: cadence: Allow to read basic xSPI configuration from ACPI Witold Sadowski (4): spi: cadence: Ensure data lines set to low during dummy-cycle period spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI spi: cadence: Add Marvell xSPI IP overlay changes spi: cadence: Add MRVL overlay xfer operation support .../devicetree/bindings/spi/cdns,xspi.yaml | 38 +- drivers/spi/spi-cadence-xspi.c | 620 +++++++++++++++++- 2 files changed, 631 insertions(+), 27 deletions(-) -- 2.43.0