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From: Shawn Sung <shawn.sung@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Bibby Hsieh <bibby.hsieh@mediatek.com>,
	CK Hu <ck.hu@mediatek.com>,
	"Nancy . Lin" <nancy.lin@mediatek.com>,
	Sean Paul <sean@poorly.run>,
	Jason Chen <jason-ch.chen@mediatek.corp-partner.google.com>,
	Fei Shao <fshao@chromium.org>, <dri-devel@lists.freedesktop.org>,
	<linux-mediatek@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Hsiao Chien Sung <shawn.sung@mediatek.com>
Subject: [PATCH v8 05/16] drm/mediatek: Set DRM mode configs accordingly
Date: Thu, 6 Jun 2024 17:26:24 +0800	[thread overview]
Message-ID: <20240606092635.27981-6-shawn.sung@mediatek.com> (raw)
In-Reply-To: <20240606092635.27981-1-shawn.sung@mediatek.com>

From: Hsiao Chien Sung <shawn.sung@mediatek.com>

Set DRM mode configs limitation according to the hardware capabilities
and pass the IGT checks as below:

- The test "graphics.IgtKms.kms_plane" requires a frame buffer with
  width of 4512 pixels (> 4096).
- The test "graphics.IgtKms.kms_cursor_crc" checks if the cursor size is
  defined, and run the test with cursor size from 1x1 to 512x512.

Please notice that the test conditions may change as IGT is updated.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |  4 ++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 8e047043202b..c9cad3a82737 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -294,6 +294,9 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
 	.conn_routes = mt8188_mtk_ddp_main_routes,
 	.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
 	.mmsys_dev_num = 2,
+	.max_width = 8191,
+	.min_width = 1,
+	.min_height = 1,
 };
 
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
@@ -308,6 +311,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
 	.main_path = mt8195_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
 	.mmsys_dev_num = 2,
+	.max_width = 8191,
+	.min_width = 1,
+	.min_height = 1,
 };
 
 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
@@ -315,6 +321,9 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
 	.mmsys_id = 1,
 	.mmsys_dev_num = 2,
+	.max_width = 8191,
+	.min_width = 2, /* 2-pixel align when ethdr is bypassed */
+	.min_height = 1,
 };
 
 static const struct of_device_id mtk_drm_of_ids[] = {
@@ -493,6 +502,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 		for (j = 0; j < private->data->mmsys_dev_num; j++) {
 			priv_n = private->all_drm_private[j];
 
+			if (priv_n->data->max_width)
+				drm->mode_config.max_width = priv_n->data->max_width;
+
+			if (priv_n->data->min_width)
+				drm->mode_config.min_width = priv_n->data->min_width;
+
+			if (priv_n->data->min_height)
+				drm->mode_config.min_height = priv_n->data->min_height;
+
 			if (i == CRTC_MAIN && priv_n->data->main_len) {
 				ret = mtk_crtc_create(drm, priv_n->data->main_path,
 						      priv_n->data->main_len, j,
@@ -520,6 +538,10 @@ static int mtk_drm_kms_init(struct drm_device *drm)
 		}
 	}
 
+	/* IGT will check if the cursor size is configured */
+	drm->mode_config.cursor_width = drm->mode_config.max_width;
+	drm->mode_config.cursor_height = drm->mode_config.max_height;
+
 	/* Use OVL device for all DMA memory allocations */
 	crtc = drm_crtc_from_index(drm, 0);
 	if (crtc)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 78d698ede1bf..6cfa790e8df5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -46,6 +46,10 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 	unsigned int mmsys_id;
 	unsigned int mmsys_dev_num;
+
+	int max_width;
+	int min_width;
+	int min_height;
 };
 
 struct mtk_drm_private {
-- 
2.18.0


  parent reply	other threads:[~2024-06-06  9:26 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-06  9:26 [PATCH v8 00/16] Support IGT in display driver Shawn Sung
2024-06-06  9:26 ` [PATCH v8 01/16] soc: mediatek: Disable 9-bit alpha in ETHDR Shawn Sung
2024-06-06  9:26 ` [PATCH v8 02/16] drm/mediatek: Add OVL compatible name for MT8195 Shawn Sung
2024-06-06  9:26 ` [PATCH v8 03/16] drm/mediatek: Add missing plane settings when async update Shawn Sung
2024-06-06  9:26 ` [PATCH v8 04/16] drm/mediatek: Add DRM_MODE_ROTATE_0 to rotation property Shawn Sung
2024-06-06  9:26 ` Shawn Sung [this message]
2024-06-10  8:14   ` [PATCH v8 05/16] drm/mediatek: Set DRM mode configs accordingly AngeloGioacchino Del Regno
2024-06-06  9:26 ` [PATCH v8 06/16] drm/mediatek: Turn off the layers with zero width or height Shawn Sung
2024-06-06  9:26 ` [PATCH v8 07/16] drm/mediatek: Support more 10bit formats in OVL Shawn Sung
2024-06-10  8:14   ` AngeloGioacchino Del Regno
2024-06-06  9:26 ` [PATCH v8 08/16] drm/mediatek: Support RGBA8888 and RGBX8888 in OVL on MT8195 Shawn Sung
2024-06-10  8:14   ` AngeloGioacchino Del Regno
2024-06-11  8:10   ` CK Hu (胡俊光)
2024-06-06  9:26 ` [PATCH v8 09/16] drm/mediatek: Support "None" blending in OVL Shawn Sung
2024-06-11  8:06   ` CK Hu (胡俊光)
2024-06-06  9:26 ` [PATCH v8 10/16] drm/mediatek: Support "None" blending in Mixer Shawn Sung
2024-06-11  9:01   ` CK Hu (胡俊光)
2024-06-06  9:26 ` [PATCH v8 11/16] drm/mediatek: Support "Pre-multiplied" blending in OVL Shawn Sung
2024-06-11  9:39   ` CK Hu (胡俊光)
2024-06-06  9:26 ` [PATCH v8 12/16] drm/mediatek: Support "Pre-multiplied" blending in Mixer Shawn Sung
2024-06-11 10:05   ` CK Hu (胡俊光)
2024-06-06  9:26 ` [PATCH v8 13/16] drm/mediatek: Support alpha blending in display driver Shawn Sung
2024-06-06  9:26 ` [PATCH v8 14/16] drm/mediatek: Support CRC " Shawn Sung
2024-06-12  1:22   ` CK Hu (胡俊光)
2024-06-21  7:27     ` Jason-JH Lin (林睿祥)
2024-06-15 21:21   ` kernel test robot
2024-06-06  9:26 ` [PATCH v8 15/16] drm/mediatek: Support CRC in OVL Shawn Sung
2024-06-12  1:35   ` CK Hu (胡俊光)
2024-06-21  9:57     ` Jason-JH Lin (林睿祥)
2024-06-06  9:26 ` [PATCH v8 16/16] drm/mediatek: Support CRC in OVL adaptor Shawn Sung

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