From: Jesse Taube <jesse@rivosinc.com>
To: linux-riscv@lists.infradead.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor.dooley@microchip.com>,
Nam Cao <namcaov@gmail.com>,
Sami Tolvanen <samitolvanen@google.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Andy Chiu <andy.chiu@sifive.com>,
Jesse Taube <jesse@rivosinc.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH] RISC-V: fix vector insn load/store width mask
Date: Thu, 6 Jun 2024 14:28:00 -0400 [thread overview]
Message-ID: <20240606182800.415831-1-jesse@rivosinc.com> (raw)
RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
Replace GENMASK(3, 0) with GENMASK(2, 0).
Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
Signed-off-by: Jesse Taube <jesse@rivosinc.com>
---
arch/riscv/include/asm/insn.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 06e439eeef9a..09fde95a5e8f 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -145,7 +145,7 @@
/* parts of opcode for RVF, RVD and RVQ */
#define RVFDQ_FL_FS_WIDTH_OFF 12
-#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0)
+#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0)
#define RVFDQ_FL_FS_WIDTH_W 2
#define RVFDQ_FL_FS_WIDTH_D 3
#define RVFDQ_LS_FS_WIDTH_Q 4
--
2.43.0
next reply other threads:[~2024-06-06 18:28 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-06 18:28 Jesse Taube [this message]
2024-06-06 18:59 ` Charlie Jenkins
2024-06-26 14:21 ` patchwork-bot+linux-riscv
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