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(pool-108-26-179-17.bstnma.fios.verizon.net. [108.26.179.17]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f855e7ca78sm17471015ad.106.2024.06.13.12.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jun 2024 12:16:34 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Evan Green , Andrew Jones , Jesse Taube , Charlie Jenkins , Xiao Wang , Andy Chiu , Eric Biggers , Greentime Hu , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Heiko Stuebner , Costa Shulyupin , Andrew Morton , Baoquan He , Anup Patel , Zong Li , Sami Tolvanen , Ben Dooks , Alexandre Ghiti , "Gustavo A. R. Silva" , Erick Archer , Joel Granados , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 0/6] RISC-V: Detect and report speed of unaligned vector accesses Date: Thu, 13 Jun 2024 15:16:09 -0400 Message-ID: <20240613191616.2101821-1-jesse@rivosinc.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Adds support for detecting and reporting the speed of unaligned vector accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe adds Zicclsm to cpufeature and fixes the check for scalar unaligned emulated all CPUs. The vec_misaligned_speed key keeps the same format as the scalar unaligned access speed key. This set does not emulate unaligned vector accesses on CPUs that do not support them. Only reports if userspace can run them and speed of unaligned vector accesses if supported. If Zicclsm is present, the kernel will set both scalar and vector unaligned access speed to FAST. This patch requires the following patche to be applied first: RISC-V: fix vector insn load/store width mask https://lore.kernel.org/all/20240606182800.415831-1-jesse@rivosinc.com/ Jesse Taube (6): RISC-V: Add Zicclsm to cpufeature and hwprobe dt-bindings: riscv: Add Zicclsm ISA extension description. RISC-V: Check scalar unaligned access on all CPUs RISC-V: Detect unaligned vector accesses supported. RISC-V: Report vector unaligned access speed hwprobe RISC-V: hwprobe: Document unaligned vector perf key Documentation/arch/riscv/hwprobe.rst | 19 +++ .../devicetree/bindings/riscv/extensions.yaml | 7 + arch/riscv/Kconfig | 59 +++++++ arch/riscv/include/asm/cpufeature.h | 7 +- arch/riscv/include/asm/entry-common.h | 11 -- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/asm/vector.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 6 + arch/riscv/kernel/Makefile | 7 +- arch/riscv/kernel/copy-unaligned.h | 5 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/sys_hwprobe.c | 48 ++++++ arch/riscv/kernel/traps_misaligned.c | 142 +++++++++++++--- arch/riscv/kernel/unaligned_access_speed.c | 154 +++++++++++++++++- arch/riscv/kernel/vec-copy-unaligned.S | 58 +++++++ arch/riscv/kernel/vector.c | 2 +- 17 files changed, 484 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/kernel/vec-copy-unaligned.S -- 2.43.0