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([2401:4900:1c28:4b16:65cf:ef28:5753:2be4]) by smtp.googlemail.com with ESMTPSA id d2e1a72fcca58-705ccb3d2acsm3717839b3a.124.2024.06.14.19.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 19:15:33 -0700 (PDT) From: Kanak Shilledar To: Cc: kanakshilledar111@protonmail.com, Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [RESEND v4 2/2] dt-bindings: riscv: cpus: add ref to interrupt-controller Date: Sat, 15 Jun 2024 07:45:04 +0530 Message-ID: <20240615021507.122035-3-kanakshilledar@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240615021507.122035-1-kanakshilledar@gmail.com> References: <20240615021507.122035-1-kanakshilledar@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit removed the redundant properties for interrupt-controller and provide reference to the riscv,cpu-intc.yaml which defines the interrupt-controller. making the properties for riscv interrupt-controller at a central place. Reviewed-by: Conor Dooley Signed-off-by: Kanak Shilledar --- Changes in v4: - Change DCO email to @gmail.com Changes in v3: - No change. - Rolling out as RESEND. Changes in v2: - Fix warning of `type` is a required property during `make dt_bindings_check`. --- .../devicetree/bindings/riscv/cpus.yaml | 21 +------------------ 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..f1241e5e8753 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -102,26 +102,7 @@ properties: interrupt-controller: type: object - additionalProperties: false - description: Describes the CPU's local interrupt controller - - properties: - '#interrupt-cells': - const: 1 - - compatible: - oneOf: - - items: - - const: andestech,cpu-intc - - const: riscv,cpu-intc - - const: riscv,cpu-intc - - interrupt-controller: true - - required: - - '#interrupt-cells' - - compatible - - interrupt-controller + $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array -- 2.45.2