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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-441ef3d89ddsm46912991cf.15.2024.06.17.07.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 07:55:21 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1sJDlR-008oz2-1P; Mon, 17 Jun 2024 11:55:21 -0300 Date: Mon, 17 Jun 2024 11:55:21 -0300 From: Jason Gunthorpe To: Zong Li Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, tjeznach@rivosinc.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, kevin.tian@intel.com, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [RFC PATCH v2 01/10] iommu/riscv: add RISC-V IOMMU PMU support Message-ID: <20240617145521.GE791043@ziepe.ca> References: <20240614142156.29420-1-zong.li@sifive.com> <20240614142156.29420-2-zong.li@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240614142156.29420-2-zong.li@sifive.com> On Fri, Jun 14, 2024 at 10:21:47PM +0800, Zong Li wrote: > This patch implements the RISC-V IOMMU hardware performance monitor, it > includes the counting ans sampling mode. > > Specification doesn't define the event ID for counting the number of > clock cycles, there is no associated iohpmevt0. But we need an event for > counting cycle in perf, reserve the maximum number of event ID for it now. Why is this part of the nesting series? Jason