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[142.68.80.239]) by smtp.gmail.com with ESMTPSA id af79cd13be357-798abc0719fsm613804685a.83.2024.06.19.08.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jun 2024 08:12:55 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.95) (envelope-from ) id 1sJwzW-004nFq-WF; Wed, 19 Jun 2024 12:12:55 -0300 Date: Wed, 19 Jun 2024 12:12:54 -0300 From: Jason Gunthorpe To: Lu Baolu Cc: Joerg Roedel , Will Deacon , Robin Murphy , Kevin Tian , Yi Liu , David Airlie , Daniel Vetter , Kalle Valo , Bjorn Andersson , Mathieu Poirier , Alex Williamson , mst@redhat.com, Jason Wang , Thierry Reding , Jonathan Hunter , Mikko Perttunen , Jeff Johnson , ath10k@lists.infradead.org, ath11k@lists.infradead.org, iommu@lists.linux.dev, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 15/21] iommu/vt-d: Add helper to allocate paging domain Message-ID: <20240619151254.GI1091770@ziepe.ca> References: <20240610085555.88197-1-baolu.lu@linux.intel.com> <20240610085555.88197-16-baolu.lu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240610085555.88197-16-baolu.lu@linux.intel.com> On Mon, Jun 10, 2024 at 04:55:49PM +0800, Lu Baolu wrote: > The domain_alloc_user operation is currently implemented by allocating a > paging domain using iommu_domain_alloc(). This is because it needs to fully > initialize the domain before return. Add a helper to do this to avoid using > iommu_domain_alloc(). > > Signed-off-by: Lu Baolu > --- > drivers/iommu/intel/iommu.c | 87 +++++++++++++++++++++++++++++++++---- > 1 file changed, 78 insertions(+), 9 deletions(-) It seems Ok, but I have some small thoughts Reviewed-by: Jason Gunthorpe > diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c > index 2e9811bf2a4e..ccde5f5972e4 100644 > --- a/drivers/iommu/intel/iommu.c > +++ b/drivers/iommu/intel/iommu.c > @@ -3633,6 +3633,79 @@ static struct iommu_domain blocking_domain = { > } > }; > > +static int iommu_superpage_capability(struct intel_iommu *iommu, bool first_stage) > +{ > + if (!intel_iommu_superpage) > + return 0; > + > + if (first_stage) > + return cap_fl1gp_support(iommu->cap) ? 2 : 1; > + > + return fls(cap_super_page_val(iommu->cap)); > +} > + > +static struct dmar_domain *paging_domain_alloc(struct device *dev, bool first_stage) > +{ > + struct device_domain_info *info = dev_iommu_priv_get(dev); > + struct intel_iommu *iommu = info->iommu; > + struct dmar_domain *domain; > + int addr_width; > + > + domain = kzalloc(sizeof(*domain), GFP_KERNEL); > + if (!domain) > + return ERR_PTR(-ENOMEM); > + > + INIT_LIST_HEAD(&domain->devices); > + INIT_LIST_HEAD(&domain->dev_pasids); > + INIT_LIST_HEAD(&domain->cache_tags); > + spin_lock_init(&domain->lock); > + spin_lock_init(&domain->cache_lock); > + xa_init(&domain->iommu_array); You should probably split more, with an 'alloc struct dmar_domain' function that can be used by SVA and others too. > + domain->nid = dev_to_node(dev); > + domain->has_iotlb_device = info->ats_enabled; > + domain->use_first_level = first_stage; > + > + /* calculate the address width */ > + addr_width = agaw_to_width(iommu->agaw); > + if (addr_width > cap_mgaw(iommu->cap)) > + addr_width = cap_mgaw(iommu->cap); > + domain->gaw = addr_width; > + domain->agaw = iommu->agaw; > + domain->max_addr = __DOMAIN_MAX_ADDR(addr_width); > + > + /* iommu memory access coherency */ > + domain->iommu_coherency = iommu_paging_structure_coherency(iommu); > + > + /* pagesize bitmap */ > + domain->domain.pgsize_bitmap = SZ_4K; > + domain->iommu_superpage = iommu_superpage_capability(iommu, first_stage); > + domain->domain.pgsize_bitmap |= domain_super_pgsize_bitmap(domain); Then some of this stuff is really just paging only. Like SVA/identity/etc don't have pgszie and other things. Jason