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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fcf48b4c7sm81900066b.86.2024.06.21.05.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jun 2024 05:54:44 -0700 (PDT) Date: Fri, 21 Jun 2024 14:54:43 +0200 From: Andrew Jones To: Samuel Holland Cc: linux-riscv@lists.infradead.org, Palmer Dabbelt , Conor Dooley , linux-kernel@vger.kernel.org, Deepak Gupta Subject: Re: [PATCH v2 0/3] riscv: Per-thread envcfg CSR support Message-ID: <20240621-368af6395900f29559358915@orel> References: <20240613171447.3176616-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240613171447.3176616-1-samuel.holland@sifive.com> On Thu, Jun 13, 2024 at 10:14:38AM GMT, Samuel Holland wrote: > This series (or equivalent) is a prerequisite for both user-mode pointer > masking and CFI support, as those are per-thread features are controlled > by fields in the envcfg CSR. These patches are based on v1 of the > pointer masking series[1], with significant input from both Deepak and > Andrew. By sending this as a separate series, hopefully we can converge > on a single implementation of this functionality. > > [1]: https://lore.kernel.org/linux-riscv/20240319215915.832127-6-samuel.holland@sifive.com/ > > Changes in v2: > - Rebase on riscv/linux.git for-next > > Samuel Holland (3): > riscv: Enable cbo.zero only when all harts support Zicboz > riscv: Add support for per-thread envcfg CSR values > riscv: Call riscv_user_isa_enable() only on the boot hart > For the series, Reviewed-by: Andrew Jones Thanks, drew