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R. Silva" , Jonathan Corbet , Paul Walmsley , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 0/2] RISC-V: hwprobe: Misaligned scalar perf fix and rename Date: Tue, 25 Jun 2024 09:51:19 -0700 Message-Id: <20240625165121.2160354-1-evan@rivosinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The CPUPERF0 hwprobe key was documented and identified in code as a bitmask value, but its contents were an enum. This produced incorrect behavior in conjunction with the WHICH_CPUS hwprobe flag. The first patch in this series fixes the bitmask/enum problem by creating a new hwprobe key that returns the same data, but is properly described as a value instead of a bitmask. The second patch renames the value definitions in preparation for adding vector misaligned access info. The second patch has the side effect of causing users using the old key values to fail to compile, which may allow them to see and update to the new key without breaking binary compatibility with old programs. Changes in v2: - Clarified the distinction of slow and fast refers to misaligned word accesses. Previously it just said misaligned accesses, leaving it ambiguous as to which type of access was measured. - Removed shifts in values (Andrew) - Renamed key to RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF (Palmer) - Added patch to rename misaligned perf key values (Palmer) Evan Green (2): RISC-V: hwprobe: Add MISALIGNED_PERF key RISC-V: hwprobe: Add SCALAR to misaligned perf defines Documentation/arch/riscv/hwprobe.rst | 29 +++++++++++++--------- arch/riscv/include/asm/hwprobe.h | 2 +- arch/riscv/include/uapi/asm/hwprobe.h | 13 +++++----- arch/riscv/kernel/sys_hwprobe.c | 11 ++++---- arch/riscv/kernel/traps_misaligned.c | 6 ++--- arch/riscv/kernel/unaligned_access_speed.c | 12 ++++----- 6 files changed, 40 insertions(+), 33 deletions(-) -- 2.34.1