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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2c99a95197asm10732198a91.16.2024.07.09.18.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jul 2024 18:16:48 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id F398980B36; Wed, 10 Jul 2024 09:26:13 +0800 (CST) From: Cheng Ming Lin To: miquel.raynal@bootlin.com, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: richard@nod.at, alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH 0/3] Add fixups for two-plane serial NAND flash Date: Wed, 10 Jul 2024 09:15:38 +0800 Message-Id: <20240710011541.342682-1-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Cheng Ming Lin Macronix serial NAND flash with a two-plane structure requires insertion of Plane Select bit into the column address during the write_to_cache operation. Additionally, for MX35{U,F}2G14AC, insertion of Plane Select bit into the column address is required during the read_from_cache operation. In spinand.h, add struct spi_nand_fixups as SPI NAND fixup hooks. In macronix.c, add fixup functions and update ID table. In core.c, add an if statement to determine whether to insert the Plane Select bit for the column address. These flashes have been validated on Xilinx zynq-picozed board which included Macronix SPI Host. Cheng Ming Lin (3): include/linux/mtd/spinand.h: Add fixups for spinand mtd: spinand: macronix: Fixups for PLANE_SELECT_BIT mtd: spinand: Insert Plane Select bit for the column address drivers/mtd/nand/spi/core.c | 7 +++++ drivers/mtd/nand/spi/macronix.c | 51 +++++++++++++++++++++++++++++---- include/linux/mtd/spinand.h | 17 +++++++++++ 3 files changed, 69 insertions(+), 6 deletions(-) -- 2.25.1