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From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Stanimir Varbanov <svarbanov@suse.de>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	james.quinlan@broadcom.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v4 12/12] PCI: brcmstb: Enable 7712 SOCs
Date: Tue, 16 Jul 2024 17:31:27 -0400	[thread overview]
Message-ID: <20240716213131.6036-13-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20240716213131.6036-1-james.quinlan@broadcom.com>

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The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Tested-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index fa5616a56383..7debb3599789 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1193,6 +1193,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
 	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
 	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
 
+	/* 7712 does not have this (RGR1) timer */
+	if (pcie->model == BCM7712)
+		return;
+
 	/* Each unit in timeout register is 1/216,000,000 seconds */
 	writel(216 * timeout_us, pcie->base + REG_OFFSET);
 }
@@ -1664,6 +1668,13 @@ static const int pcie_offsets_bmips_7425[] = {
 	[PCIE_INTR2_CPU_BASE] = 0x4300,
 };
 
+static const int pcie_offset_bcm7712[] = {
+	[EXT_CFG_INDEX]  = 0x9000,
+	[EXT_CFG_DATA]   = 0x9004,
+	[PCIE_HARD_DEBUG] = 0x4304,
+	[PCIE_INTR2_CPU_BASE] = 0x4400,
+};
+
 static const struct pcie_cfg_data generic_cfg = {
 	.offsets	= pcie_offsets,
 	.model		= GENERIC,
@@ -1729,6 +1740,14 @@ static const struct pcie_cfg_data bcm7216_cfg = {
 	.num_inbound	= 3,
 };
 
+static const struct pcie_cfg_data bcm7712_cfg = {
+	.offsets	= pcie_offset_bcm7712,
+	.perst_set	= brcm_pcie_perst_set_7278,
+	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+	.model		= BCM7712,
+	.num_inbound	= 10,
+};
+
 static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
 	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1738,6 +1757,7 @@ static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
 	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
 	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+	{ .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
 	{},
 };
 
-- 
2.17.1


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  parent reply	other threads:[~2024-07-16 21:32 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-16 21:31 [PATCH v4 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 01/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-07-17  6:51   ` Krzysztof Kozlowski
2024-07-17 13:20     ` Jim Quinlan
2024-07-17 13:30       ` Krzysztof Kozlowski
2024-07-23 18:49         ` Jim Quinlan
2024-07-17 21:06     ` Florian Fainelli
2024-07-18  6:02       ` Krzysztof Kozlowski
2024-07-18  6:07       ` Krzysztof Kozlowski
2024-07-23 18:44     ` Jim Quinlan
2024-07-24  8:05       ` Krzysztof Kozlowski
2024-07-24 18:57         ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 02/12] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-07-17  6:52   ` Krzysztof Kozlowski
2024-07-23 21:03     ` Jim Quinlan
2024-07-24  6:02       ` Krzysztof Kozlowski
2024-07-16 21:31 ` [PATCH v4 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-07-25  4:31   ` Manivannan Sadhasivam
2024-07-25 19:45     ` Jim Quinlan
2024-07-26  5:04       ` Manivannan Sadhasivam
2024-07-26 18:34         ` Jim Quinlan
2024-07-27  6:40           ` Manivannan Sadhasivam
2024-07-29 15:24             ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-25  4:37   ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-25  4:39   ` Manivannan Sadhasivam
2024-07-29 21:49     ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-25  4:43   ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-25  4:43   ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-25  4:48   ` Manivannan Sadhasivam
2024-07-26 19:03     ` Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-07-25  4:53   ` Manivannan Sadhasivam
2024-07-25 20:29     ` Jim Quinlan
2024-07-26  5:08       ` Manivannan Sadhasivam
2024-07-16 21:31 ` [PATCH v4 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-07-16 21:31 ` [PATCH v4 11/12] PCI: brcmstb: Change field name from 'type' to 'model' Jim Quinlan
2024-07-25  4:58   ` Manivannan Sadhasivam
2024-07-25 20:38     ` Jim Quinlan
2024-07-26 11:29       ` Manivannan Sadhasivam
2024-07-16 21:31 ` Jim Quinlan [this message]
2024-07-25  4:59   ` [PATCH v4 12/12] PCI: brcmstb: Enable 7712 SOCs Manivannan Sadhasivam
2024-07-25  5:03 ` [PATCH v4 00/12] PCI: brcnstb: Enable STB 7712 SOC Manivannan Sadhasivam

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