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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar Subject: Re: [PATCH 5/6] drivers/thermal/exynos: add initial Exynos 850 support Date: Tue, 23 Jul 2024 16:16:54 +0200 Message-ID: <20240723141658.374755-1-m.majewski2@samsung.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsWy7djP87qJu+enGez9a27xYN42NovvW64z WazZe47JYt5nWYv5R86xWpw/v4HdYtPja6wWl3fNYbP43HuE0WLG+X1MFgubWtgtJh6bzGwx 98tUZov/e3awWzx52Mdm8bxvH5ODgMeaeWsYPXbOusvusXjPSyaPTas62TzuXNvD5rF5Sb1H 35ZVjB6fN8kFcERx2aSk5mSWpRbp2yVwZVw8/Jqx4KhwxdwTjxkbGE/zdzFyckgImEgcPPmZ sYuRi0NIYAWjxJXJPSwQzhdGiXOvZjJBOJ8ZJd6uaGeBadk39yMrRGI5o0Rz33Oo/lYmif+H z4NVsQkYSDx4s4wdxBYR0JNYN/MVO0gRs8BmFokLT2eygiSEBQIlzq9pAmrg4GARUJU4vYgb JMwrYCvx5T7IUSDb5CV69/cxgdicQOX3nnSxQdQISpyc+QRsFzNQTfPW2cwg8yUE+jklNq29 yQ4yU0LAReLOHDGIOcISr45vYYewZST+75zPBGHnS8zY/J4ForxC4u5BLwjTWuLjGWYQk1lA U2L9Ln2IYkeJ71NuQc3mk7jxVhBiP5/EpG3TmSHCvBIdbUIQ1aoSx/dMYoawpSWetNxmgijx kJg3k3UCo+IsJI/MQvLILIS1CxiZVzGKp5YW56anFhvmpZbrFSfmFpfmpesl5+duYgSmtdP/ jn/awTj31Ue9Q4xMHIyHGCU4mJVEeJ+8mpsmxJuSWFmVWpQfX1Sak1p8iFGag0VJnFc1RT5V SCA9sSQ1OzW1ILUIJsvEwSnVwKSn1MlsonP+pat5xMe7b1fVREkbbfjMmO9V0csbYKAvz7R9 66Sn9w9+nvr6vQ//pcYvzvJ6Ahc2lz99auN7MyxrelfSjPf++v8+nTScGpzNuUhwdrvIqdn3 2Z01A/fuumB2Zuqea+y5c30Kb53zDIm1uH6l6LJyi8HF/5Uy11QY72vo3FjY8lau2KNriZ4D q8/qAPlt8+ZJWW84vHH+xEyFr4k2aYaL491qz83btc5jZ6pQ0ualb9p9yhWsTvzaH3i59brA rA3LeYQSRH2ObFjjNldJ3vLhit05N3Y935f41+cY7wvhMIc93oUpoleDV7R4rCxL5FPUCP31 2XR2RAm7//aZWabTF8sujT3FFqXEUpyRaKjFXFScCAAXJoJv2gMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBIsWRmVeSWpSXmKPExsVy+t/xe7qJu+enGaxfL27xYN42NovvW64z WazZe47JYt5nWYv5R86xWpw/v4HdYtPja6wWl3fNYbP43HuE0WLG+X1MFgubWtgtJh6bzGwx 98tUZov/e3awWzx52Mdm8bxvH5ODgMeaeWsYPXbOusvusXjPSyaPTas62TzuXNvD5rF5Sb1H 35ZVjB6fN8kFcETp2RTll5akKmTkF5fYKkUbWhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSW pRbp2yXoZVw8/Jqx4KhwxdwTjxkbGE/zdzFyckgImEjsm/uRFcQWEljKKLHvdxBEXFri8Jcp 7BC2sMSfa11sEDXNTBJ/J1WD2GwCBhIP3iwDqxER0JNYN/MVkM3FwSxwkEWi7/UVZpCEsIC/ xPcL7SxdjBwcLAKqEqcXcYOEeQVsJb7c/8wIMV9eond/HxOIzSkQKHHvCcwuHolXG/YzQtQL Spyc+YQFxGYGqm/eOpt5AqPALCSpWUhSCxiZVjGKpJYW56bnFhvpFSfmFpfmpesl5+duYgRG 4bZjP7fsYFz56qPeIUYmDsZDjBIczEoivE9ezU0T4k1JrKxKLcqPLyrNSS0+xGgKdPZEZinR 5HxgGsgriTc0MzA1NDGzNDC1NDNWEuf1LOhIFBJITyxJzU5NLUgtgulj4uCUamDaHP/0sz7L bHGlNqnVJfZRUfPY9lmwHwtfecKz2StU6e3J9IrpLZeuJB7dc5WJ0/Kw1rRtTAqHfl/dFFVU UVcw84FRe95csZRz7InlD5btrOJb5V8z2bB/+/4pt6qcPmibtAZ2VDh/YP5q7M1z/tbmOT/u rPGTXdF+lLFHoCnL/vyMf79Y7dq3f/wj+l7ZPsrhwhUepXmz3ipcdxbU8jk25avKBy3pjYHP IvOT5zMyrL+0MWlP1InGgmltC+eIdkhPP/Sm6dyE12WytpoTZvEGOCQvVk1jvHlIaX9sidPE v70H7q0wYbryvkB+6e0Srhf+5QWtecoLcm5tdlgmzBtU87D+sOojv/WyB+abfwpVYinOSDTU Yi4qTgQA5JGYSUsDAAA= X-CMS-MailID: 20240723141705eucas1p1bbe72a6d543031a41efdbe81d1b03ac3 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20240723141705eucas1p1bbe72a6d543031a41efdbe81d1b03ac3 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20240723141705eucas1p1bbe72a6d543031a41efdbe81d1b03ac3 References: > Do you know what are the possible implications of not using ACPM? As I > understand, ACPM is a Samsung's downstream framework which uses APM > (Active Power Management) IP block internally to act as an IPC > mechanism, which makes it possible to offload any PM related > operations (which might get quite heavy, if we are to belive the TRM > description of APM) from CPU to APM. I'm not against the direct > registers access based implementation (in fact, I'm not sure how that > APM/ACPM thing can be implemented in upstreamable way and if it's > worth it at all). Just curious if we understand what we are > potentially missing out, and if at some point we'll be forced to > implement that ACPM thing anyway (for something else)? Not sure honestly. The downstream v4.10 driver does many operations on registers anyway...? > Not sure if that's true, as already discussed in my comments for the > previous patches. Looks like one clock is still needed, which is the > PCLK bus clock (to interface registers) which might simultaneously act > as an operating (functional) clock. The code seems to be working correctly without this clock, both register reads and writes. Maybe the support for extra sensors, which I couldn't get to work, would require this clock? > Exynos850 TRM says AVG_CONTROL offset is 0x38, and 0x58 is actually > for THRESHOLD0_TEMP_RISE3_2 register. Thank you so much! Will fix in v2. Though writing to the right place doesn't seem to change much in practice, probably just means that the correct mode is being used. > Something seems off to me here. How come the shift value for EXYNOS7 > case is 8, but the mask is actually 9 bits long? Does it mean the > first error field is 8 bits long, and the second error field is 9 bits > long for EXYNOS7? I don't have the Exynos7 manual, so it's just a > hunch. But if it's true, maybe this shift value has to be added in > your [PATCH 2/6] to fix Exynos7 case? I did not really want to mess with Exynos7 code, as we don't have an Exynos7 board sadly. Honestly I feel like I should drop the 2/6 patch completely and only modify the code to run on 850 correctly. > Also, just an idea: those values (and other similar values) could be > pre-calculated somewhere during the probe, stored in some struct (e.g. > _variant or _chip) and then just used here. sanitize_temp_error is only called one per probe and once per resume, so probably little to gain? Will also do all other.