From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94AA614F9DA; Thu, 1 Aug 2024 00:10:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722471014; cv=none; b=slQdrf/AtzYCodxE+DqelGWHHCOOnr2O6CzstWOv7g8wsfQ22IUm2SvELpvESUWDVbhm8nTKGoo+yna8d/F++QY0EJrWsKFIlj81bo1INGodqM5NpMKPoieDFCCXF4YgMaumAnXDe1OvltnfGFFhrkZhhRSP7LjoSfyxxutP9IY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722471014; c=relaxed/simple; bh=W3oUaL901wpWKL883MvvjPg/OCyqaTMhpUbRlCxZ0QI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mZYw1lnKSGvYHprzVsKPUoj25ti77SqYX5y0eUyGXSW+BgIaZxDNYym89TZb2xFjXFWNJHcdntKEZt7QrvtzkladCLfblKxg2nOVJBzN6JahzoY5JCHLopPmYDbM1z7GR7z1KJb47CFbCwqcuGWAxRB5uH7COwVRuRowmzbHC9o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mjYyM5so; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mjYyM5so" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B8D7C32786; Thu, 1 Aug 2024 00:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722471014; bh=W3oUaL901wpWKL883MvvjPg/OCyqaTMhpUbRlCxZ0QI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mjYyM5soyJOVBBNmVJvLX2C4I6OV/HvrdAw6IQTnMl+L0JFediCbTJY4AhHRgr/GR OB/bwTda4Qx7S4Auno9IHNBU/JpAFwBkH44a/5Wysr8uNUlAtkpwlfEbsQLTMF6f7M MIFRMmuizv70/dF4f25Zbb+CEL0pZ1Rpu+N6wlKzPLV2m035KQxvRKyHVLa0e654xZ Qm8T7V6oYdLGVzB1kahUDAJ2hQRqqqLjciBmvRIJ9Vxw0Aot3X1AAiOosdCLU1TfEJ cr9iyAhvEfkPvdAKvRfE+PD1AMo8+3y9zGg+dNQQCSyMjsOojXpZg59SDa7bloCXus OCeTxUIXyqOMQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Alex Hung , Harry Wentland , Tom Chung , Daniel Wheeler , Alex Deucher , Sasha Levin , sunpeng.li@amd.com, Rodrigo.Siqueira@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, roman.li@amd.com, hamza.mahfooz@amd.com, aric.cyr@amd.com, joshua.aberback@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.10 018/121] drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[] Date: Wed, 31 Jul 2024 19:59:16 -0400 Message-ID: <20240801000834.3930818-18-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240801000834.3930818-1-sashal@kernel.org> References: <20240801000834.3930818-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.10.2 Content-Transfer-Encoding: 8bit From: Alex Hung [ Upstream commit b38a4815f79b87efb196cd5121579fc51e29a7fb ] [WHY & HOW] num_valid_sets needs to be checked to avoid a negative index when accessing reader_wm_sets[num_valid_sets - 1]. This fixes an OVERRUN issue reported by Coverity. Reviewed-by: Harry Wentland Acked-by: Tom Chung Signed-off-by: Alex Hung Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c index 5ef0879f6ad9c..aea4bb46856ef 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c @@ -484,7 +484,8 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; /* Modify previous watermark range to cover up to max */ - ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; + if (num_valid_sets > 0) + ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; } num_valid_sets++; } -- 2.43.0