From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD9A814A4F7; Thu, 1 Aug 2024 00:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722470944; cv=none; b=RMIpjvh36nLsGSdyrKRPfbre2uEYppP4SvhsJeh4qbpW9j+GVOxq396qmJFaPKWph3ZFy8XI3JC+7lxc0Mej82tjucdsmw25NJtiuBiYgRnkZ1G+3aHJDsNjwaNvruZxHTBBISNI8PaTlQAr4us1Q16/9+1IszdEgtvYPsBbTMc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722470944; c=relaxed/simple; bh=it8x9H8/prFHuG9kp3jDVCpzNe8HqqP/uXTNWzbv2no=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=taVqh92Tc/+dXBiEtmaYTZBCTuB93QRwp6JeFs222ZD2x0j8BYQfo0Z3FToxbe3AALqtmMMJ+DZ5eedFs6kaaBN48SuoObCE/q1PszqO/ubK/NMSZLNyPNarWOah3KtsITk5XecgyF8rVaTrq1wZPFXLh/NUwzVUw6ceb3kcz7A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dSw/7ObZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dSw/7ObZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 391F6C116B1; Thu, 1 Aug 2024 00:09:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1722470944; bh=it8x9H8/prFHuG9kp3jDVCpzNe8HqqP/uXTNWzbv2no=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dSw/7ObZNVEolvJ9mIOqOxHN3AgbRO6nVZ7OmZBgJJp5+eE2mIeBBt9u9oeg0ssQs bMo8ocxb7lUGFOxpKofM2xzQH0R8LK8Xy+XRhbygbubW8HKSnsYR9hghhIYIVHggYq W6sYXS2IEL4wnCxzcnIA9ikesl10kOoktJ9G8S0NWrD1BbdslhLzJbQfE9Kc4C/Maz 2T5ChxnOeFmBC8ZoVHL6QLIHqIZXVhxsq03C0EpeyAiPwAIrRaXSd4V+2H7m20urFG owOuw+zG+i0GbP1MC3a5cBLsFKqyedixiK1ngckFCEyZJ6cEnK1518o1NoijINIe+X fUKnnyrap6TNQ== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Jesse Zhang , Jesse Zhang , Tim Huang , Alex Deucher , Sasha Levin , kenneth.feng@amd.com, christian.koenig@amd.com, Xinhui.Pan@amd.com, airlied@gmail.com, daniel@ffwll.ch, Jun.Ma2@amd.com, kevinyang.wang@amd.com, mario.limonciello@amd.com, lijo.lazar@amd.com, yifan1.zhang@amd.com, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 6.10 006/121] drm/amd/pm: Fix negative array index read Date: Wed, 31 Jul 2024 19:59:04 -0400 Message-ID: <20240801000834.3930818-6-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240801000834.3930818-1-sashal@kernel.org> References: <20240801000834.3930818-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.10.2 Content-Transfer-Encoding: 8bit From: Jesse Zhang [ Upstream commit c8c19ebf7c0b202a6a2d37a52ca112432723db5f ] Avoid using the negative values for clk_idex as an index into an array pptable->DpmDescriptor. V2: fix clk_index return check (Tim Huang) Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 27 ++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index 5a68d365967f7..c06e0d6e30177 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -1219,19 +1219,22 @@ static int navi10_get_current_clk_freq_by_table(struct smu_context *smu, value); } -static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) +static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type) { PPTable_t *pptable = smu->smu_table.driver_pptable; DpmDescriptor_t *dpm_desc = NULL; - uint32_t clk_index = 0; + int clk_index = 0; clk_index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_CLK, clk_type); + if (clk_index < 0) + return clk_index; + dpm_desc = &pptable->DpmDescriptor[clk_index]; /* 0 - Fine grained DPM, 1 - Discrete DPM */ - return dpm_desc->SnapToDiscrete == 0; + return dpm_desc->SnapToDiscrete == 0 ? 1 : 0; } static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap) @@ -1287,7 +1290,11 @@ static int navi10_emit_clk_levels(struct smu_context *smu, if (ret) return ret; - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + ret = navi10_is_support_fine_grained_dpm(smu, clk_type); + if (ret < 0) + return ret; + + if (!ret) { for (i = 0; i < count; i++) { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); @@ -1496,7 +1503,11 @@ static int navi10_print_clk_levels(struct smu_context *smu, if (ret) return size; - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { + ret = navi10_is_support_fine_grained_dpm(smu, clk_type); + if (ret < 0) + return ret; + + if (!ret) { for (i = 0; i < count; i++) { ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value); if (ret) @@ -1665,7 +1676,11 @@ static int navi10_force_clk_levels(struct smu_context *smu, case SMU_UCLK: case SMU_FCLK: /* There is only 2 levels for fine grained DPM */ - if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { + ret = navi10_is_support_fine_grained_dpm(smu, clk_type); + if (ret < 0) + return ret; + + if (ret) { soft_max_level = (soft_max_level >= 1 ? 1 : 0); soft_min_level = (soft_min_level >= 1 ? 1 : 0); } -- 2.43.0