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From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
	tony.luck@intel.com, x86@kernel.org, avadhut.naik@amd.com,
	john.allen@amd.com
Subject: Re: [PATCH 7/9] x86/mce: Unify AMD DFR handler with MCA Polling
Date: Fri, 16 Aug 2024 10:08:53 -0400	[thread overview]
Message-ID: <20240816140853.GB29375@yaz-khff2.amd.com> (raw)
In-Reply-To: <20240604110528.GRZl70-MFo-EikWRHs@fat_crate.local>

On Tue, Jun 04, 2024 at 01:05:28PM +0200, Borislav Petkov wrote:
> On Thu, May 23, 2024 at 10:56:39AM -0500, Yazen Ghannam wrote:
> > +static bool smca_log_poll_error(struct mce *m, u32 *status_reg)
> 
> That handing of *status_reg back'n'forth just to clear it in the end is
> not nice. Let's get rid of it:
> 
> ---
> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
> index 0a9cff329487..a0ba82fe6de3 100644
> --- a/arch/x86/kernel/cpu/mce/core.c
> +++ b/arch/x86/kernel/cpu/mce/core.c
> @@ -669,7 +669,7 @@ static void reset_thr_limit(unsigned int bank)
>  
>  DEFINE_PER_CPU(unsigned, mce_poll_count);
>  
> -static bool smca_log_poll_error(struct mce *m, u32 *status_reg)
> +static bool smca_log_poll_error(struct mce *m, u32 status_reg)
>  {
>  	/*
>  	 * If this is a deferred error found in MCA_STATUS, then clear
> @@ -686,8 +686,8 @@ static bool smca_log_poll_error(struct mce *m, u32 *status_reg)
>  	 * If the MCA_DESTAT register has valid data, then use
>  	 * it as the status register.
>  	 */
> -	*status_reg = MSR_AMD64_SMCA_MCx_DESTAT(m->bank);
> -	m->status = mce_rdmsrl(*status_reg);
> +	status_reg = MSR_AMD64_SMCA_MCx_DESTAT(m->bank);
> +	m->status = mce_rdmsrl(status_reg);
>  
>  	if (!(m->status & MCI_STATUS_VAL))
>  		return false;
> @@ -695,6 +695,8 @@ static bool smca_log_poll_error(struct mce *m, u32 *status_reg)
>  	if (m->status & MCI_STATUS_ADDRV)
>  		m->addr = mce_rdmsrl(MSR_AMD64_SMCA_MCx_DEADDR(m->bank));
>  
> +	mce_wrmsrl(status_reg, 0);
> +

I had to think on this for a while. The reason to clear the status
register at the very end is to make sure another error doesn't come in
and overwrite all the "aux" registers before we grab them.

***BUT*** the reason we are going down this path is because another
(higher priority) error *did* overwrite everything. And we're trying to
gather any leftover data. So all the "aux" registers are already
out-of-sync.

I don't think we can solve this in software. We'd need all the state
registers to be duplicated in hardware. We have status and address which
seem to be enough.

I'll see if this can be simplified even further.

Thanks,
Yazen

  reply	other threads:[~2024-08-16 14:09 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-23 15:56 [PATCH 0/9] AMD MCA interrupts rework Yazen Ghannam
2024-05-23 15:56 ` [PATCH 1/9] x86/mce/inject: Only write MCA_MISC with user-set value Yazen Ghannam
2024-05-27  9:00   ` [tip: ras/core] x86/mce/inject: Only write MCA_MISC when a value has been supplied tip-bot2 for Yazen Ghannam
2024-05-23 15:56 ` [PATCH 2/9] x86/mce: Remove unused variable and return value in machine_check_poll() Yazen Ghannam
2024-05-27  9:00   ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2024-05-23 15:56 ` [PATCH 3/9] x86/mce: Increment MCP count only for timer calls Yazen Ghannam
2024-05-24 14:53   ` Borislav Petkov
2024-06-03 14:22     ` Yazen Ghannam
2024-06-03 15:24       ` Borislav Petkov
2024-05-23 15:56 ` [PATCH 4/9] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2024-06-03 17:37   ` Borislav Petkov
2024-07-26 14:00     ` Yazen Ghannam
2024-08-01 13:04       ` Borislav Petkov
2024-05-23 15:56 ` [PATCH 5/9] x86/mce: Skip AMD threshold init if no threshold banks found Yazen Ghannam
2024-05-23 15:56 ` [PATCH 6/9] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2024-06-03 18:04   ` Borislav Petkov
2024-08-16 14:01     ` Yazen Ghannam
2024-05-23 15:56 ` [PATCH 7/9] x86/mce: Unify AMD DFR " Yazen Ghannam
2024-06-04 11:05   ` Borislav Petkov
2024-08-16 14:08     ` Yazen Ghannam [this message]
2024-06-04 11:18   ` Borislav Petkov
2024-05-23 15:56 ` [PATCH 8/9] x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems Yazen Ghannam
2024-06-04 15:46   ` Borislav Petkov
2024-08-16 14:17     ` Yazen Ghannam
2024-05-23 15:56 ` [PATCH 9/9] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam

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