[PATCH v1 11/12] nvmem: microchip-otpc: Enable main RC oscillator clock

[Alexander Dahl <ada@thorsis.com>]

Without enabling that clock, initializing the packet list leads to a
read timeout on the first packet.

According to SAM9X60 datasheet (DS60001579G) section "23.4 Product
Dependencies" the clock must be enabled for reading and writing.

Tested on sam9x60-curiosity board.

Signed-off-by: Alexander Dahl <ada@thorsis.com>
---
 drivers/nvmem/microchip-otpc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c
index a80535c3d162..047ca5ac6407 100644
--- a/drivers/nvmem/microchip-otpc.c
+++ b/drivers/nvmem/microchip-otpc.c
@@ -8,6 +8,7 @@
  */
 
 #include <linux/bitfield.h>
+#include <linux/clk.h>
 #include <linux/dev_printk.h>
 #include <linux/iopoll.h>
 #include <linux/module.h>
@@ -54,6 +55,7 @@
 struct mchp_otpc {
 	void __iomem *base;
 	struct device *dev;
+	struct clk *clk;
 	struct list_head packets;
 	u32 npackets;
 };
@@ -272,6 +274,15 @@ static int mchp_otpc_probe(struct platform_device *pdev)
 	if (IS_ERR(otpc->base))
 		return PTR_ERR(otpc->base);
 
+	// NOTE: Maybe make this optional, especially if sama7g5 testing
+	// shows the clock is not required there?
+	otpc->clk = devm_clk_get_enabled(&pdev->dev, "main_rc_osc");
+	if (IS_ERR(otpc->clk)) {
+		dev_err(&pdev->dev, "Error (%ld) getting clock!\n",
+			PTR_ERR(otpc->clk));
+		return PTR_ERR(otpc->clk);
+	}
+
 	reg = readl_relaxed(otpc->base + MCHP_OTPC_WPSR);
 	if (reg)
 		dev_warn(&pdev->dev,
-- 
2.39.2