mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Steven Price <steven.price@arm.com>
To: kvm@vger.kernel.org, kvmarm@lists.linux.dev
Cc: Jean-Philippe Brucker <jean-philippe@linaro.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
	James Morse <james.morse@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	Fuad Tabba <tabba@google.com>,
	linux-coco@lists.linux.dev,
	Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
	Gavin Shan <gshan@redhat.com>,
	Shanker Donthineni <sdonthineni@nvidia.com>,
	Alper Gun <alpergun@google.com>,
	Steven Price <steven.price@arm.com>
Subject: [PATCH v4 41/43] arm64: RME: Provide accurate register list
Date: Wed, 21 Aug 2024 16:38:42 +0100	[thread overview]
Message-ID: <20240821153844.60084-42-steven.price@arm.com> (raw)
In-Reply-To: <20240821153844.60084-1-steven.price@arm.com>

From: Jean-Philippe Brucker <jean-philippe@linaro.org>

Userspace can set a few registers with KVM_SET_ONE_REG (9 GP registers
at runtime, and 3 system registers during initialization). Update the
register list returned by KVM_GET_REG_LIST.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Steven Price <steven.price@arm.com>
---
 arch/arm64/kvm/guest.c      | 40 ++++++++++++++++++-------
 arch/arm64/kvm/hypercalls.c |  4 +--
 arch/arm64/kvm/sys_regs.c   | 58 ++++++++++++++++++++++++++++---------
 3 files changed, 75 insertions(+), 27 deletions(-)

diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index b12b5e4ddd8c..1ac0a552550c 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -73,6 +73,17 @@ static u64 core_reg_offset_from_id(u64 id)
 	return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
 }
 
+static bool kvm_realm_validate_core_reg(u64 off)
+{
+	switch (off) {
+	case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
+	     KVM_REG_ARM_CORE_REG(regs.regs[7]):
+	case KVM_REG_ARM_CORE_REG(regs.pc):
+		return true;
+	}
+	return false;
+}
+
 static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
 {
 	int size;
@@ -115,6 +126,9 @@ static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off)
 	if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off))
 		return -EINVAL;
 
+	if (kvm_is_realm(vcpu->kvm) && !kvm_realm_validate_core_reg(off))
+		return -EPERM;
+
 	return size;
 }
 
@@ -600,8 +614,6 @@ static const u64 timer_reg_list[] = {
 	KVM_REG_ARM_PTIMER_CVAL,
 };
 
-#define NUM_TIMER_REGS ARRAY_SIZE(timer_reg_list)
-
 static bool is_timer_reg(u64 index)
 {
 	switch (index) {
@@ -616,9 +628,14 @@ static bool is_timer_reg(u64 index)
 	return false;
 }
 
+static unsigned long num_timer_regs(struct kvm_vcpu *vcpu)
+{
+	return kvm_is_realm(vcpu->kvm) ? 0 : ARRAY_SIZE(timer_reg_list);
+}
+
 static int copy_timer_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 {
-	for (int i = 0; i < NUM_TIMER_REGS; i++) {
+	for (int i = 0; i < num_timer_regs(vcpu); i++) {
 		if (put_user(timer_reg_list[i], uindices))
 			return -EFAULT;
 		uindices++;
@@ -656,6 +673,9 @@ static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu)
 	if (!vcpu_has_sve(vcpu) || !kvm_arm_vcpu_sve_finalized(vcpu))
 		return 0;
 
+	if (kvm_is_realm(vcpu->kvm))
+		return 1; /* KVM_REG_ARM64_SVE_VLS */
+
 	return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */)
 		+ 1; /* KVM_REG_ARM64_SVE_VLS */
 }
@@ -683,6 +703,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu,
 		return -EFAULT;
 	++num_regs;
 
+	if (kvm_is_realm(vcpu->kvm))
+		return num_regs;
+
 	for (i = 0; i < slices; i++) {
 		for (n = 0; n < SVE_NUM_ZREGS; n++) {
 			reg = KVM_REG_ARM64_SVE_ZREG(n, i);
@@ -721,7 +744,7 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
 	res += num_sve_regs(vcpu);
 	res += kvm_arm_num_sys_reg_descs(vcpu);
 	res += kvm_arm_get_fw_num_regs(vcpu);
-	res += NUM_TIMER_REGS;
+	res += num_timer_regs(vcpu);
 
 	return res;
 }
@@ -755,7 +778,7 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 	ret = copy_timer_indices(vcpu, uindices);
 	if (ret < 0)
 		return ret;
-	uindices += NUM_TIMER_REGS;
+	uindices += num_timer_regs(vcpu);
 
 	return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
 }
@@ -795,12 +818,7 @@ static bool validate_realm_set_reg(struct kvm_vcpu *vcpu,
 	if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE) {
 		u64 off = core_reg_offset_from_id(reg->id);
 
-		switch (off) {
-		case KVM_REG_ARM_CORE_REG(regs.regs[0]) ...
-		     KVM_REG_ARM_CORE_REG(regs.regs[7]):
-		case KVM_REG_ARM_CORE_REG(regs.pc):
-			return true;
-		}
+		return kvm_realm_validate_core_reg(off);
 	} else {
 		switch (reg->id) {
 		case KVM_REG_ARM_PMCR_EL0:
diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c
index 5763d979d8ca..28b4166cf234 100644
--- a/arch/arm64/kvm/hypercalls.c
+++ b/arch/arm64/kvm/hypercalls.c
@@ -407,14 +407,14 @@ void kvm_arm_teardown_hypercalls(struct kvm *kvm)
 
 int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu)
 {
-	return ARRAY_SIZE(kvm_arm_fw_reg_ids);
+	return kvm_is_realm(vcpu->kvm) ? 0 : ARRAY_SIZE(kvm_arm_fw_reg_ids);
 }
 
 int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 {
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) {
+	for (i = 0; i < kvm_arm_get_fw_num_regs(vcpu); i++) {
 		if (put_user(kvm_arm_fw_reg_ids[i], uindices++))
 			return -EFAULT;
 	}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f92b78039dce..3510c7a684f1 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -4357,18 +4357,18 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg
 				    sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
 }
 
-static unsigned int num_demux_regs(void)
+static unsigned int num_demux_regs(struct kvm_vcpu *vcpu)
 {
-	return CSSELR_MAX;
+	return kvm_is_realm(vcpu->kvm) ? 0 : CSSELR_MAX;
 }
 
-static int write_demux_regids(u64 __user *uindices)
+static int write_demux_regids(struct kvm_vcpu *vcpu, u64 __user *uindices)
 {
 	u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
 	unsigned int i;
 
 	val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
-	for (i = 0; i < CSSELR_MAX; i++) {
+	for (i = 0; i < num_demux_regs(vcpu); i++) {
 		if (put_user(val | i, uindices))
 			return -EFAULT;
 		uindices++;
@@ -4376,6 +4376,23 @@ static int write_demux_regids(u64 __user *uindices)
 	return 0;
 }
 
+static unsigned int num_invariant_regs(struct kvm_vcpu *vcpu)
+{
+	return kvm_is_realm(vcpu->kvm) ? 0 : ARRAY_SIZE(invariant_sys_regs);
+}
+
+static int write_invariant_regids(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+	unsigned int i;
+
+	for (i = 0; i < num_invariant_regs(vcpu); i++) {
+		if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
+			return -EFAULT;
+		uindices++;
+	}
+	return 0;
+}
+
 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
 {
 	return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
@@ -4399,11 +4416,27 @@ static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
 	return true;
 }
 
+static bool kvm_realm_sys_reg_hidden_user(const struct kvm_vcpu *vcpu, u64 reg)
+{
+	if (!kvm_is_realm(vcpu->kvm))
+		return false;
+
+	switch (reg) {
+	case SYS_ID_AA64DFR0_EL1:
+	case SYS_PMCR_EL0:
+		return false;
+	}
+	return true;
+}
+
 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
 			    const struct sys_reg_desc *rd,
 			    u64 __user **uind,
 			    unsigned int *total)
 {
+	if (kvm_realm_sys_reg_hidden_user(vcpu, reg_to_encoding(rd)))
+		return 0;
+
 	/*
 	 * Ignore registers we trap but don't save,
 	 * and for which no custom user accessor is provided.
@@ -4441,29 +4474,26 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
 
 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
 {
-	return ARRAY_SIZE(invariant_sys_regs)
-		+ num_demux_regs()
+	return num_invariant_regs(vcpu)
+		+ num_demux_regs(vcpu)
 		+ walk_sys_regs(vcpu, (u64 __user *)NULL);
 }
 
 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 {
-	unsigned int i;
 	int err;
 
-	/* Then give them all the invariant registers' indices. */
-	for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
-		if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
-			return -EFAULT;
-		uindices++;
-	}
+	err = write_invariant_regids(vcpu, uindices);
+	if (err)
+		return err;
+	uindices += num_invariant_regs(vcpu);
 
 	err = walk_sys_regs(vcpu, uindices);
 	if (err < 0)
 		return err;
 	uindices += err;
 
-	return write_demux_regids(uindices);
+	return write_demux_regids(vcpu, uindices);
 }
 
 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r)			\
-- 
2.34.1


  parent reply	other threads:[~2024-08-21 15:41 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-21 15:38 [PATCH v4 00/43] arm64: Support for Arm CCA in KVM Steven Price
2024-08-21 15:38 ` [PATCH v4 01/43] KVM: Prepare for handling only shared mappings in mmu_notifier events Steven Price
2024-08-21 15:38 ` [PATCH v4 02/43] kvm: arm64: pgtable: Track the number of pages in the entry level Steven Price
2024-08-21 15:38 ` [PATCH v4 03/43] kvm: arm64: Include kvm_emulate.h in kvm/arm_psci.h Steven Price
2024-08-21 15:38 ` [PATCH v4 04/43] arm64: RME: Handle Granule Protection Faults (GPFs) Steven Price
2024-08-21 15:38 ` [PATCH v4 05/43] arm64: RME: Add SMC definitions for calling the RMM Steven Price
2024-08-22 15:44   ` Suzuki K Poulose
2024-09-06  0:11   ` Gavin Shan
2024-09-08 23:56     ` Gavin Shan
2024-08-21 15:38 ` [PATCH v4 06/43] arm64: RME: Add wrappers for RMI calls Steven Price
2024-08-22 16:56   ` Suzuki K Poulose
2024-08-21 15:38 ` [PATCH v4 07/43] arm64: RME: Check for RME support at KVM init Steven Price
2024-09-12  8:49   ` Gavin Shan
2024-09-12  9:27     ` Steven Price
2024-08-21 15:38 ` [PATCH v4 08/43] arm64: RME: Define the user ABI Steven Price
2024-08-21 15:38 ` [PATCH v4 09/43] arm64: RME: ioctls to create and configure realms Steven Price
2024-09-06 19:05   ` Shanker Donthineni
2024-09-10 10:43     ` Suzuki K Poulose
2024-08-21 15:38 ` [PATCH v4 10/43] kvm: arm64: Expose debug HW register numbers for Realm Steven Price
2024-08-21 15:38 ` [PATCH v4 11/43] arm64: kvm: Allow passing machine type in KVM creation Steven Price
2024-08-21 15:38 ` [PATCH v4 12/43] arm64: RME: Keep a spare page delegated to the RMM Steven Price
2024-08-21 15:38 ` [PATCH v4 13/43] arm64: RME: RTT tear down Steven Price
2024-08-21 15:38 ` [PATCH v4 14/43] arm64: RME: Allocate/free RECs to match vCPUs Steven Price
2024-08-21 15:38 ` [PATCH v4 15/43] arm64: RME: Support for the VGIC in realms Steven Price
2024-08-21 15:38 ` [PATCH v4 16/43] KVM: arm64: Support timers in realm RECs Steven Price
2024-08-21 15:38 ` [PATCH v4 17/43] arm64: RME: Allow VMM to set RIPAS Steven Price
2024-08-21 15:38 ` [PATCH v4 18/43] arm64: RME: Handle realm enter/exit Steven Price
2024-08-22  3:53   ` Aneesh Kumar K.V
2024-08-22 15:05     ` Steven Price
2024-08-22  3:58   ` Aneesh Kumar K.V
2024-08-22 15:05     ` Steven Price
2024-08-22  4:04   ` Aneesh Kumar K.V
2024-08-22 15:06     ` Steven Price
2024-08-22 14:14   ` kernel test robot
2024-08-21 15:38 ` [PATCH v4 19/43] KVM: arm64: Handle realm MMIO emulation Steven Price
2024-08-21 15:38 ` [PATCH v4 20/43] arm64: RME: Allow populating initial contents Steven Price
2024-08-21 15:38 ` [PATCH v4 21/43] arm64: RME: Runtime faulting of memory Steven Price
2024-08-22  3:32   ` Aneesh Kumar K.V
2024-08-22 15:14     ` Steven Price
2024-08-22  3:50   ` Aneesh Kumar K.V
2024-08-22 15:40     ` Steven Price
2024-08-23  4:30       ` Aneesh Kumar K.V
2024-09-02 13:25   ` Matias Ezequiel Vara Larsen
2024-09-02 15:34     ` Steven Price
2024-09-04 14:48   ` Jean-Philippe Brucker
2024-09-04 15:59     ` Steven Price
2024-08-21 15:38 ` [PATCH v4 22/43] KVM: arm64: Handle realm VCPU load Steven Price
2024-08-21 15:38 ` [PATCH v4 23/43] KVM: arm64: Validate register access for a Realm VM Steven Price
2024-08-21 15:38 ` [PATCH v4 24/43] KVM: arm64: Handle Realm PSCI requests Steven Price
2024-08-21 15:38 ` [PATCH v4 25/43] KVM: arm64: WARN on injected undef exceptions Steven Price
2024-08-21 15:38 ` [PATCH v4 26/43] arm64: Don't expose stolen time for realm guests Steven Price
2024-08-21 15:38 ` [PATCH v4 27/43] arm64: rme: allow userspace to inject aborts Steven Price
2024-08-21 15:38 ` [PATCH v4 28/43] arm64: rme: support RSI_HOST_CALL Steven Price
2024-08-21 15:38 ` [PATCH v4 29/43] arm64: rme: Allow checking SVE on VM instance Steven Price
2024-08-21 15:38 ` [PATCH v4 30/43] arm64: RME: Always use 4k pages for realms Steven Price
2024-08-21 15:38 ` [PATCH v4 31/43] arm64: rme: Prevent Device mappings for Realms Steven Price
2024-08-21 15:38 ` [PATCH v4 32/43] arm_pmu: Provide a mechanism for disabling the physical IRQ Steven Price
2024-08-21 15:38 ` [PATCH v4 33/43] arm64: rme: Enable PMU support with a realm guest Steven Price
2024-08-21 15:38 ` [PATCH v4 34/43] kvm: rme: Hide KVM_CAP_READONLY_MEM for realm guests Steven Price
2024-08-21 15:38 ` [PATCH v4 35/43] arm64: RME: Propagate number of breakpoints and watchpoints to userspace Steven Price
2024-08-21 15:38 ` [PATCH v4 36/43] arm64: RME: Set breakpoint parameters through SET_ONE_REG Steven Price
2024-08-21 15:38 ` [PATCH v4 37/43] arm64: RME: Initialize PMCR.N with number counter supported by RMM Steven Price
2024-08-21 15:38 ` [PATCH v4 38/43] arm64: RME: Propagate max SVE vector length from RMM Steven Price
2024-08-21 15:38 ` [PATCH v4 39/43] arm64: RME: Configure max SVE vector length for a Realm Steven Price
2024-08-21 15:38 ` [PATCH v4 40/43] arm64: RME: Provide register list for unfinalized RME RECs Steven Price
2024-08-21 15:38 ` Steven Price [this message]
2024-08-21 15:38 ` [PATCH v4 42/43] arm64: kvm: Expose support for private memory Steven Price
2024-08-21 15:38 ` [PATCH v4 43/43] KVM: arm64: Allow activating realms Steven Price
2024-09-02  5:13   ` Aneesh Kumar K.V
2024-09-02 10:17     ` Steven Price

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240821153844.60084-42-steven.price@arm.com \
    --to=steven.price@arm.com \
    --cc=alexandru.elisei@arm.com \
    --cc=alpergun@google.com \
    --cc=catalin.marinas@arm.com \
    --cc=christoffer.dall@arm.com \
    --cc=gankulkarni@os.amperecomputing.com \
    --cc=gshan@redhat.com \
    --cc=james.morse@arm.com \
    --cc=jean-philippe@linaro.org \
    --cc=joey.gouly@arm.com \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.linux.dev \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-coco@lists.linux.dev \
    --cc=linux-kernel@vger.kernel.org \
    --cc=maz@kernel.org \
    --cc=oliver.upton@linux.dev \
    --cc=sdonthineni@nvidia.com \
    --cc=suzuki.poulose@arm.com \
    --cc=tabba@google.com \
    --cc=will@kernel.org \
    --cc=yuzenghui@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®