Re: [PATCH 07/11] pinctrl: rp1: Implement RaspberryPi RP1 gpio support

[kernel test robot <lkp@intel.com>]

Hi Andrea,

kernel test robot noticed the following build errors:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on robh/for-next char-misc/char-misc-testing char-misc/char-misc-next char-misc/char-misc-linus linus/master v6.11-rc4 next-20240821]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Andrea-della-Porta/dt-bindings-clock-Add-RaspberryPi-RP1-clock-bindings/20240821-023901
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/eb39a5f3cefff2a1240a18a255dac090af16f223.1724159867.git.andrea.porta%40suse.com
patch subject: [PATCH 07/11] pinctrl: rp1: Implement RaspberryPi RP1 gpio support
config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20240821/202408211907.cUrf3RpN-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240821/202408211907.cUrf3RpN-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202408211907.cUrf3RpN-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/pinctrl/pinctrl-rp1.c: In function 'rp1_get_fsel':
>> drivers/pinctrl/pinctrl-rp1.c:237:22: error: implicit declaration of function 'FIELD_GET'; did you mean 'FIELD_SET'? [-Werror=implicit-function-declaration]
     237 |         u32 oeover = FIELD_GET(RP1_GPIO_CTRL_OEOVER_MASK, ctrl);
         |                      ^~~~~~~~~
         |                      FIELD_SET
   drivers/pinctrl/pinctrl-rp1.c: In function 'rp1_set_fsel':
>> drivers/pinctrl/pinctrl-rp1.c:146:25: error: implicit declaration of function 'FIELD_PREP'; did you mean 'FIELD_SET'? [-Werror=implicit-function-declaration]
     146 |                 _reg |= FIELD_PREP((_mask), (_val));    \
         |                         ^~~~~~~~~~
   drivers/pinctrl/pinctrl-rp1.c:257:17: note: in expansion of macro 'FIELD_SET'
     257 |                 FIELD_SET(ctrl, RP1_GPIO_CTRL_OEOVER_MASK, RP1_OEOVER_DISABLE);
         |                 ^~~~~~~~~
   cc1: some warnings being treated as errors


vim +237 drivers/pinctrl/pinctrl-rp1.c

   136	
   137	#define RP1_PAD_DRIVE_2MA		0x00000000
   138	#define RP1_PAD_DRIVE_4MA		BIT(4)
   139	#define RP1_PAD_DRIVE_8MA		BIT(5)
   140	#define RP1_PAD_DRIVE_12MA		(RP1_PAD_DRIVE_4MA | \
   141						RP1_PAD_DRIVE_8MA)
   142	
   143	#define FIELD_SET(_reg, _mask, _val)			\
   144		({						\
   145			_reg &= ~(_mask);				\
 > 146			_reg |= FIELD_PREP((_mask), (_val));	\
   147		})
   148	
   149	#define FUNC(f) \
   150		[func_##f] = #f
   151	
   152	struct rp1_iobank_desc {
   153		int min_gpio;
   154		int num_gpios;
   155		int gpio_offset;
   156		int inte_offset;
   157		int ints_offset;
   158		int rio_offset;
   159		int pads_offset;
   160	};
   161	
   162	struct rp1_pin_info {
   163		u8 num;
   164		u8 bank;
   165		u8 offset;
   166		u8 fsel;
   167		u8 irq_type;
   168	
   169		void __iomem *gpio;
   170		void __iomem *rio;
   171		void __iomem *inte;
   172		void __iomem *ints;
   173		void __iomem *pad;
   174	};
   175	
   176	struct rp1_pinctrl {
   177		struct device *dev;
   178		void __iomem *gpio_base;
   179		void __iomem *rio_base;
   180		void __iomem *pads_base;
   181		int irq[RP1_NUM_BANKS];
   182		struct rp1_pin_info pins[RP1_NUM_GPIOS];
   183	
   184		struct pinctrl_dev *pctl_dev;
   185		struct gpio_chip gpio_chip;
   186		struct pinctrl_gpio_range gpio_range;
   187	
   188		raw_spinlock_t irq_lock[RP1_NUM_BANKS];
   189	};
   190	
   191	const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = {
   192		/*         gpio   inte    ints     rio    pads */
   193		{  0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 },
   194		{ 28,  6, 0x4000, 0x411c, 0x4124, 0x4000, 0x4004 },
   195		{ 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 },
   196	};
   197	
   198	static int rp1_pinconf_set(struct rp1_pin_info *pin,
   199				   unsigned int offset, unsigned long *configs,
   200				   unsigned int num_configs);
   201	
   202	static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip,
   203						unsigned int offset)
   204	{
   205		struct rp1_pinctrl *pc = gpiochip_get_data(chip);
   206	
   207		if (pc && offset < RP1_NUM_GPIOS)
   208			return &pc->pins[offset];
   209		return NULL;
   210	}
   211	
   212	static void rp1_pad_update(struct rp1_pin_info *pin, u32 clr, u32 set)
   213	{
   214		u32 padctrl = readl(pin->pad);
   215	
   216		padctrl &= ~clr;
   217		padctrl |= set;
   218	
   219		writel(padctrl, pin->pad);
   220	}
   221	
   222	static void rp1_input_enable(struct rp1_pin_info *pin, int value)
   223	{
   224		rp1_pad_update(pin, RP1_PAD_IN_ENABLE_MASK,
   225			       value ? RP1_PAD_IN_ENABLE_MASK : 0);
   226	}
   227	
   228	static void rp1_output_enable(struct rp1_pin_info *pin, int value)
   229	{
   230		rp1_pad_update(pin, RP1_PAD_OUT_DISABLE_MASK,
   231			       value ? 0 : RP1_PAD_OUT_DISABLE_MASK);
   232	}
   233	
   234	static u32 rp1_get_fsel(struct rp1_pin_info *pin)
   235	{
   236		u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
 > 237		u32 oeover = FIELD_GET(RP1_GPIO_CTRL_OEOVER_MASK, ctrl);
   238		u32 fsel = FIELD_GET(RP1_GPIO_CTRL_FUNCSEL_MASK, ctrl);
   239	
   240		if (oeover != RP1_OEOVER_PERI || fsel >= RP1_FSEL_COUNT)
   241			fsel = RP1_FSEL_NONE;
   242	
   243		return fsel;
   244	}
   245	

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