From: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH v2 3/6] drm/msm/a6xx: Store correct gmu_cgc_mode in struct a6xx_info
Date: Wed, 28 Aug 2024 17:06:56 +0200 [thread overview]
Message-ID: <20240828-topic-a621-v2-3-1882c6b57432@kernel.org> (raw)
In-Reply-To: <20240828-topic-a621-v2-0-1882c6b57432@kernel.org>
From: Konrad Dybcio <konrad.dybcio@linaro.org>
Store the correct values that we happen to have for some A7xx SKUs in
the GPU info struct and fill out the missing information for A6xx GPUs
based on downstream kernel information.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 18 ++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 1ea535960f32..6cd73abd95d4 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -636,6 +636,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a612_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00080000,
},
/*
@@ -668,6 +669,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -691,6 +693,7 @@ static const struct adreno_info a6xx_gpus[] = {
.init = a6xx_gpu_init,
.a6xx = &(const struct a6xx_info) {
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -714,6 +717,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -737,6 +741,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -760,6 +765,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a615_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00000222,
.prim_fifo_threshold = 0x00018000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -788,6 +794,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a630_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00180000,
},
}, {
@@ -806,6 +813,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00180000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -829,6 +837,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a650_hwcg,
.protect = &a650_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
@@ -855,6 +864,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
+ .gmu_cgc_mode = 0x00020000,
.prim_fifo_threshold = 0x00300200,
},
.address_space_size = SZ_16G,
@@ -874,6 +884,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a660_hwcg,
.protect = &a660_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00200200,
},
.address_space_size = SZ_16G,
@@ -899,6 +910,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a640_hwcg,
.protect = &a630_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x00200200,
},
}, {
@@ -917,6 +929,7 @@ static const struct adreno_info a6xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a690_hwcg,
.protect = &a690_protect,
+ .gmu_cgc_mode = 0x00020200,
.prim_fifo_threshold = 0x00800200,
},
.address_space_size = SZ_16G,
@@ -1178,6 +1191,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a702_hwcg,
.protect = &a650_protect,
+ .gmu_cgc_mode = 0x00020202,
.prim_fifo_threshold = 0x0000c000,
},
.speedbins = ADRENO_SPEEDBINS(
@@ -1202,6 +1216,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.hwcg = a730_hwcg,
.protect = &a730_protect,
+ .gmu_cgc_mode = 0x00020000,
},
.address_space_size = SZ_16G,
}, {
@@ -1221,6 +1236,7 @@ static const struct adreno_info a7xx_gpus[] = {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.gmu_chipid = 0x7020100,
+ .gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_16G,
}, {
@@ -1239,6 +1255,7 @@ static const struct adreno_info a7xx_gpus[] = {
.hwcg = a740_hwcg,
.protect = &a730_protect,
.gmu_chipid = 0x7050001,
+ .gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_256G,
}, {
@@ -1257,6 +1274,7 @@ static const struct adreno_info a7xx_gpus[] = {
.a6xx = &(const struct a6xx_info) {
.protect = &a730_protect,
.gmu_chipid = 0x7090100,
+ .gmu_cgc_mode = 0x00020202,
},
.address_space_size = SZ_16G,
}
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index bc37bd8c7f65..0fb7febf70e7 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -22,6 +22,7 @@ struct a6xx_info {
const struct adreno_reglist *hwcg;
const struct adreno_protect *protect;
u32 gmu_chipid;
+ u32 gmu_cgc_mode;
u32 prim_fifo_threshold;
};
--
2.46.0
next prev parent reply other threads:[~2024-08-28 15:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-28 15:06 [PATCH v2 0/6] A621 support Konrad Dybcio
2024-08-28 15:06 ` [PATCH v2 1/6] drm/msm/a6xx: Evaluate adreno_is_a650_family in pdc_in_aop check Konrad Dybcio
2024-08-28 15:06 ` [PATCH v2 2/6] drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info Konrad Dybcio
2024-08-28 15:06 ` Konrad Dybcio [this message]
2024-08-28 15:06 ` [PATCH v2 4/6] drm/msm/a6xx: Use the per-GPU value for gmu_cgc_mode Konrad Dybcio
2024-08-28 15:06 ` [PATCH v2 5/6] drm/msm/a6xx: Set GMU CGC properties on a6xx too Konrad Dybcio
2024-08-28 15:06 ` [PATCH v2 6/6] drm/msm/a6xx: Add A621 support Konrad Dybcio
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