Re: [PATCH] usb: dwc3: core: update LC timer as per USB Spec V3.2

[Thinh Nguyen <Thinh.Nguyen@synopsys.com>]

On Thu, Aug 22, 2024, Faisal Hassan wrote:
> This fix addresses STAR 9001285599, which only affects dwc3 core version
> 320a. The timer value for PM_LC_TIMER in 320a for the Link ECN changes

When note for the controller IP and version in comments, use the IP name
and version: DWC_usb3 version 3.20a

"dwc3" is ambiguous.

> is incorrect. If the PM TIMER ECN is enabled via GUCTL2[19], the link
> compliance test (TD7.21) may fail. If the ECN is not enabled
> (GUCTL2[19] = 0), the controller will use the old timer value (5us),
> which is still acceptable for the link compliance test. Therefore, clear
> GUCTL2[19] to pass the USB link compliance test: TD 7.21.
> 
> Cc: stable@vger.kernel.org
> Signed-off-by: Faisal Hassan <quic_faisalh@quicinc.com>
> ---
>  drivers/usb/dwc3/core.c | 15 +++++++++++++++
>  drivers/usb/dwc3/core.h |  2 ++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 734de2a8bd21..d0bd3a0e1f9c 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -1378,6 +1378,21 @@ static int dwc3_core_init(struct dwc3 *dwc)
>  		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
>  	}
>  
> +	/*
> +	 * STAR 9001285599: This issue affects dwc3 core version 3.20a

Note IP name along with version.
ie. "... affects DWC_usb3 version 3.20a ..."

> +	 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the
> +	 * link compliance test (TD7.21) may fail. If the ECN is not
> +	 * enabled (GUCTL2[19] = 0), the controller will use the old timer
> +	 * value (5us), which is still acceptable for the link compliance
> +	 * test. Therefore, do not enable PM TIMER ECM in 3.20a by
> +	 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.
> +	 */
> +	if (DWC3_VER_IS(DWC3, 320A)) {
> +		reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
> +		reg &= ~DWC3_GUCTL2_LC_TIMER;
> +		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
> +	}
> +
>  	/*
>  	 * When configured in HOST mode, after issuing U3/L2 exit controller
>  	 * fails to send proper CRC checksum in CRC5 feild. Because of this
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index 1e561fd8b86e..c71240e8f7c7 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -421,6 +421,7 @@
>  
>  /* Global User Control Register 2 */
>  #define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)
> +#define DWC3_GUCTL2_LC_TIMER			BIT(19)
>  
>  /* Global User Control Register 3 */
>  #define DWC3_GUCTL3_SPLITDISABLE		BIT(14)
> @@ -1269,6 +1270,7 @@ struct dwc3 {
>  #define DWC3_REVISION_290A	0x5533290a
>  #define DWC3_REVISION_300A	0x5533300a
>  #define DWC3_REVISION_310A	0x5533310a
> +#define DWC3_REVISION_320A	0x5533320a
>  #define DWC3_REVISION_330A	0x5533330a
>  
>  #define DWC31_REVISION_ANY	0x0
> -- 
> 2.17.1
> 

After the minor fix, you can include this:

Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>

Thanks,
Thinh