From: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
To: <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <horms@kernel.org>, <saeedm@nvidia.com>,
<anthony.l.nguyen@intel.com>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <andrew@lunn.ch>,
<corbet@lwn.net>, <linux-doc@vger.kernel.org>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <devicetree@vger.kernel.org>,
<horatiu.vultur@microchip.com>, <ruanjinjie@huawei.com>,
<steen.hegelund@microchip.com>, <vladimir.oltean@nxp.com>
Cc: <parthiban.veerasooran@microchip.com>, <masahiroy@kernel.org>,
<alexanderduyck@fb.com>, <krzk+dt@kernel.org>, <robh@kernel.org>,
<rdunlap@infradead.org>, <hkallweit1@gmail.com>,
<linux@armlinux.org.uk>, <UNGLinuxDriver@microchip.com>,
<Thorsten.Kummermehr@microchip.com>, <Pier.Beruto@onsemi.com>,
<Selvamani.Rajagopal@onsemi.com>, <Nicolas.Ferre@microchip.com>,
<benjamin.bigler@bernformulastudent.ch>, <linux@bigler.io>,
<markku.vorne@kempower.com>,
Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
Subject: [PATCH net-next v7 03/14] net: ethernet: oa_tc6: implement register read operation
Date: Tue, 3 Sep 2024 16:16:54 +0530 [thread overview]
Message-ID: <20240903104705.378684-4-Parthiban.Veerasooran@microchip.com> (raw)
In-Reply-To: <20240903104705.378684-1-Parthiban.Veerasooran@microchip.com>
Implement register read operation according to the control communication
specified in the OPEN Alliance 10BASE-T1x MACPHY Serial Interface
document. Control read commands are used by the SPI host to read
registers within the MAC-PHY. Each control read commands are composed of
a 32 bits control command header.
The MAC-PHY ignores all data from the SPI host following the control
header for the remainder of the control read command. Control read
commands can read either a single register or multiple consecutive
registers. When multiple consecutive registers are read, the address is
automatically post-incremented by the MAC-PHY. Reading any unimplemented
or undefined registers shall return zero.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Parthiban Veerasooran <Parthiban.Veerasooran@microchip.com>
---
drivers/net/ethernet/oa_tc6.c | 84 ++++++++++++++++++++++++++++++++++-
include/linux/oa_tc6.h | 3 ++
2 files changed, 85 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/oa_tc6.c b/drivers/net/ethernet/oa_tc6.c
index 24e9fd92d717..72bab9234436 100644
--- a/drivers/net/ethernet/oa_tc6.c
+++ b/drivers/net/ethernet/oa_tc6.c
@@ -38,6 +38,7 @@ enum oa_tc6_header_type {
};
enum oa_tc6_register_op {
+ OA_TC6_CTRL_REG_READ = 0,
OA_TC6_CTRL_REG_WRITE = 1,
};
@@ -113,7 +114,8 @@ static void oa_tc6_prepare_ctrl_spi_buf(struct oa_tc6 *tc6, u32 address,
*tx_buf = oa_tc6_prepare_ctrl_header(address, length, reg_op);
- oa_tc6_update_ctrl_write_data(tc6, value, length);
+ if (reg_op == OA_TC6_CTRL_REG_WRITE)
+ oa_tc6_update_ctrl_write_data(tc6, value, length);
}
static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size)
@@ -132,6 +134,30 @@ static int oa_tc6_check_ctrl_write_reply(struct oa_tc6 *tc6, u8 size)
return 0;
}
+static int oa_tc6_check_ctrl_read_reply(struct oa_tc6 *tc6, u8 size)
+{
+ u32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE;
+ u32 *tx_buf = tc6->spi_ctrl_tx_buf;
+
+ /* The echoed control read header must match with the one that was
+ * transmitted.
+ */
+ if (*tx_buf != *rx_buf)
+ return -EPROTO;
+
+ return 0;
+}
+
+static void oa_tc6_copy_ctrl_read_data(struct oa_tc6 *tc6, u32 value[],
+ u8 length)
+{
+ __be32 *rx_buf = tc6->spi_ctrl_rx_buf + OA_TC6_CTRL_IGNORED_SIZE +
+ OA_TC6_CTRL_HEADER_SIZE;
+
+ for (int i = 0; i < length; i++)
+ value[i] = be32_to_cpu(*rx_buf++);
+}
+
static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[],
u8 length, enum oa_tc6_register_op reg_op)
{
@@ -152,8 +178,62 @@ static int oa_tc6_perform_ctrl(struct oa_tc6 *tc6, u32 address, u32 value[],
}
/* Check echoed/received control write command reply for errors */
- return oa_tc6_check_ctrl_write_reply(tc6, size);
+ if (reg_op == OA_TC6_CTRL_REG_WRITE)
+ return oa_tc6_check_ctrl_write_reply(tc6, size);
+
+ /* Check echoed/received control read command reply for errors */
+ ret = oa_tc6_check_ctrl_read_reply(tc6, size);
+ if (ret)
+ return ret;
+
+ oa_tc6_copy_ctrl_read_data(tc6, value, length);
+
+ return 0;
+}
+
+/**
+ * oa_tc6_read_registers - function for reading multiple consecutive registers.
+ * @tc6: oa_tc6 struct.
+ * @address: address of the first register to be read in the MAC-PHY.
+ * @value: values to be read from the starting register address @address.
+ * @length: number of consecutive registers to be read from @address.
+ *
+ * Maximum of 128 consecutive registers can be read starting at @address.
+ *
+ * Return: 0 on success otherwise failed.
+ */
+int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[],
+ u8 length)
+{
+ int ret;
+
+ if (!length || length > OA_TC6_CTRL_MAX_REGISTERS) {
+ dev_err(&tc6->spi->dev, "Invalid register length parameter\n");
+ return -EINVAL;
+ }
+
+ mutex_lock(&tc6->spi_ctrl_lock);
+ ret = oa_tc6_perform_ctrl(tc6, address, value, length,
+ OA_TC6_CTRL_REG_READ);
+ mutex_unlock(&tc6->spi_ctrl_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(oa_tc6_read_registers);
+
+/**
+ * oa_tc6_read_register - function for reading a MAC-PHY register.
+ * @tc6: oa_tc6 struct.
+ * @address: register address of the MAC-PHY to be read.
+ * @value: value read from the @address register address of the MAC-PHY.
+ *
+ * Return: 0 on success otherwise failed.
+ */
+int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value)
+{
+ return oa_tc6_read_registers(tc6, address, value, 1);
}
+EXPORT_SYMBOL_GPL(oa_tc6_read_register);
/**
* oa_tc6_write_registers - function for writing multiple consecutive registers.
diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h
index 99c490f1c8a8..85aeecf87306 100644
--- a/include/linux/oa_tc6.h
+++ b/include/linux/oa_tc6.h
@@ -15,3 +15,6 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi);
int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, u32 value);
int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, u32 value[],
u8 length);
+int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, u32 *value);
+int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, u32 value[],
+ u8 length);
--
2.34.1
next prev parent reply other threads:[~2024-09-03 10:48 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-03 10:46 [PATCH net-next v7 00/14] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Parthiban Veerasooran
2024-09-03 10:46 ` [PATCH net-next v7 01/14] Documentation: networking: add OPEN Alliance 10BASE-T1x MAC-PHY serial interface Parthiban Veerasooran
2024-09-03 10:46 ` [PATCH net-next v7 02/14] net: ethernet: oa_tc6: implement register write operation Parthiban Veerasooran
2024-09-03 10:46 ` Parthiban Veerasooran [this message]
2024-09-03 10:46 ` [PATCH net-next v7 04/14] net: ethernet: oa_tc6: implement software reset Parthiban Veerasooran
2024-09-03 10:46 ` [PATCH net-next v7 05/14] net: ethernet: oa_tc6: implement error interrupts unmasking Parthiban Veerasooran
2024-09-03 10:46 ` [PATCH net-next v7 06/14] net: ethernet: oa_tc6: implement internal PHY initialization Parthiban Veerasooran
2024-09-03 10:46 ` [PATCH net-next v7 07/14] net: phy: microchip_t1s: add c45 direct access in LAN865x internal PHY Parthiban Veerasooran
2024-09-03 10:46 ` [PATCH net-next v7 08/14] net: ethernet: oa_tc6: enable open alliance tc6 data communication Parthiban Veerasooran
2024-09-03 10:47 ` [PATCH net-next v7 09/14] net: ethernet: oa_tc6: implement transmit path to transfer tx ethernet frames Parthiban Veerasooran
2024-09-03 10:47 ` [PATCH net-next v7 10/14] net: ethernet: oa_tc6: implement receive path to receive rx " Parthiban Veerasooran
2024-09-03 10:47 ` [PATCH net-next v7 11/14] net: ethernet: oa_tc6: implement mac-phy interrupt Parthiban Veerasooran
2024-09-03 10:47 ` [PATCH net-next v7 12/14] net: ethernet: oa_tc6: add helper function to enable zero align rx frame Parthiban Veerasooran
2024-09-03 10:47 ` [PATCH net-next v7 13/14] microchip: lan865x: add driver support for Microchip's LAN865X MAC-PHY Parthiban Veerasooran
2024-09-03 19:54 ` Andrew Lunn
2024-09-03 10:47 ` [PATCH net-next v7 14/14] dt-bindings: net: add Microchip's LAN865X 10BASE-T1S MACPHY Parthiban Veerasooran
2024-09-03 14:43 ` Rob Herring
2024-09-04 12:51 ` Parthiban.Veerasooran
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