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AJvYcCXPjmmHpyI8mKsd/K+x63HEzGaUGtWlmvziqp37KSnyqdNfdCOIJfUJv93trTOiGCvoycKzzpDgR5drziQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyT5tIE8tV3UiJxYWfLExQMA563BvUIFrGRRDx6kCPZoG+Qjeae qWinEhaFqB+E38GxCXQyuuVC+8CjwCJ/08dRNbiE1Wi0FAaRDABW1K4l641NeQ== X-Google-Smtp-Source: AGHT+IGaIqW5Fd7iC7eWGx3Bkr4KIAhnl/c5JAG+0dmpw/6XA8lzo2zqW5pfYpjv80IFZFIFhT9/Sw== X-Received: by 2002:a17:902:cec6:b0:206:9caf:1e00 with SMTP id d9443c01a7336-2069caf211cmr72629265ad.25.1725464996370; Wed, 04 Sep 2024 08:49:56 -0700 (PDT) Received: from thinkpad ([120.60.128.165]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-206ae950571sm15158925ad.82.2024.09.04.08.49.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2024 08:49:56 -0700 (PDT) Date: Wed, 4 Sep 2024 21:19:44 +0530 From: Manivannan Sadhasivam To: Johan Hovold Cc: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Jingoo Han , Chuanhua Lei , Marek Vasut , Yoshihiro Shimoda , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-arm-msm@vger.kernel.org, abel.vesa@linaro.org, johan+linaro@kernel.org, Shashank Babu Chinta Venkata Subject: Re: [PATCH v6 2/4] PCI: dwc: Always cache the maximum link speed value in dw_pcie::max_link_speed Message-ID: <20240904154944.w4bujfmhy5uhzkld@thinkpad> References: <20240904-pci-qcom-gen4-stability-v6-0-ec39f7ae3f62@linaro.org> <20240904-pci-qcom-gen4-stability-v6-2-ec39f7ae3f62@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Sep 04, 2024 at 11:30:08AM +0200, Johan Hovold wrote: > On Wed, Sep 04, 2024 at 12:41:58PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > > From: Manivannan Sadhasivam > > > > Currently, dw_pcie::max_link_speed has a valid value only if the controller > > driver restricts the maximum link speed in the driver or if the platform > > does so in the devicetree using the 'max-link-speed' property. > > > > But having the maximum supported link speed of the platform would be > > helpful for the vendor drivers to configure any link specific settings. > > So in the case of non-valid value in dw_pcie::max_link_speed, just cache > > the hardware default value from Link Capability register. > > > > While at it, let's also remove the 'max_link_speed' argument to the > > dw_pcie_link_set_max_speed() function since the value can be retrieved > > within the function. > > > > Signed-off-by: Manivannan Sadhasivam > > --- > > drivers/pci/controller/dwc/pcie-designware.c | 18 ++++++++++++++---- > > 1 file changed, 14 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > > index 86c49ba097c6..0704853daa85 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > @@ -687,16 +687,27 @@ void dw_pcie_upconfig_setup(struct dw_pcie *pci) > > } > > EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); > > > > -static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 max_link_speed) > > +static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) > > { > > u32 cap, ctrl2, link_speed; > > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > > > > cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > > + > > + /* > > + * Even if the platform doesn't want to limit the maximum link speed, > > + * just cache the hardware default value so that the vendor drivers can > > + * use it to do any link specific configuration. > > + */ > > + if (pci->max_link_speed < 0) { > > This should be > > if (pci->max_link_speed < 1) { > Well I was trying to catch the error value here because if neither driver nor platform limits the max link speed, this would have -EINVAL (returned by of_pci_get_max_link_speed()). But logically it makes sense to use 'pci->max_link_speed < 1' since anything below value 1 is an invalid value. Will change it. - Mani > but the patch works as-is because of the default case in the switch > below which falls back to PCI_EXP_LNKCAP_SLS. > > > + pci->max_link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); > > + return; > > + } > > + > > ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); > > ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; > > > > - switch (pcie_link_speed[max_link_speed]) { > > + switch (pcie_link_speed[pci->max_link_speed]) { > > case PCIE_SPEED_2_5GT: > > link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; > > break; > > > @@ -1058,8 +1069,7 @@ void dw_pcie_setup(struct dw_pcie *pci) > > { > > u32 val; > > > > - if (pci->max_link_speed > 0) > > - dw_pcie_link_set_max_speed(pci, pci->max_link_speed); > > + dw_pcie_link_set_max_speed(pci); > > With the above fixed: > > Reviewed-by: Johan Hovold -- மணிவண்ணன் சதாசிவம்