From: Antonino Maniscalco <antomani103@gmail.com>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Jonathan Corbet <corbet@lwn.net>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org,
Antonino Maniscalco <antomani103@gmail.com>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: [PATCH v3 01/10] drm/msm: Fix bv_fence being used as bv_rptr
Date: Thu, 05 Sep 2024 16:51:19 +0200 [thread overview]
Message-ID: <20240905-preemption-a750-t-v3-1-fd947699f7bc@gmail.com> (raw)
In-Reply-To: <20240905-preemption-a750-t-v3-0-fd947699f7bc@gmail.com>
The bv_fence field of rbmemptrs was being used incorrectly as the BV
rptr shadow pointer in some places.
Add a bv_rptr field and change the code to use that instead.
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index bcaec86ac67a..32a4faa93d7f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1132,7 +1132,7 @@ static int hw_init(struct msm_gpu *gpu)
/* ..which means "always" on A7xx, also for BV shadow */
if (adreno_is_a7xx(adreno_gpu)) {
gpu_write64(gpu, REG_A7XX_CP_BV_RB_RPTR_ADDR,
- rbmemptr(gpu->rb[0], bv_fence));
+ rbmemptr(gpu->rb[0], bv_rptr));
}
/* Always come up on rb 0 */
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.h b/drivers/gpu/drm/msm/msm_ringbuffer.h
index 0d6beb8cd39a..40791b2ade46 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.h
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.h
@@ -31,6 +31,7 @@ struct msm_rbmemptrs {
volatile uint32_t rptr;
volatile uint32_t fence;
/* Introduced on A7xx */
+ volatile uint32_t bv_rptr;
volatile uint32_t bv_fence;
volatile struct msm_gpu_submit_stats stats[MSM_GPU_SUBMIT_STATS_COUNT];
--
2.46.0
next prev parent reply other threads:[~2024-09-05 14:51 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-05 14:51 [PATCH v3 00/10] Preemption support for A7XX Antonino Maniscalco
2024-09-05 14:51 ` Antonino Maniscalco [this message]
2024-09-05 14:51 ` [PATCH v3 02/10] drm/msm: Add a `preempt_record_size` field Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 03/10] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 04/10] drm/msm/A6xx: Implement preemption for A7XX targets Antonino Maniscalco
2024-09-06 19:54 ` Akhil P Oommen
2024-09-09 12:22 ` Connor Abbott
2024-09-10 16:43 ` Akhil P Oommen
2024-09-12 15:48 ` Antonino Maniscalco
2024-09-16 17:40 ` Akhil P Oommen
2024-09-09 13:15 ` Antonino Maniscalco
2024-09-09 13:42 ` Connor Abbott
2024-09-09 14:40 ` Rob Clark
2024-09-10 16:49 ` Akhil P Oommen
2024-09-09 17:24 ` Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 05/10] drm/msm/A6xx: Sync relevant adreno_pm4.xml changes Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 06/10] drm/msm/A6xx: Use posamble to reset counters on preemption Antonino Maniscalco
2024-09-06 20:08 ` Akhil P Oommen
2024-09-09 15:07 ` Antonino Maniscalco
2024-09-10 21:34 ` Akhil P Oommen
2024-09-10 22:35 ` Antonino Maniscalco
2024-09-12 7:12 ` Akhil P Oommen
2024-09-12 11:15 ` Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 07/10] drm/msm/A6xx: Add traces for preemption Antonino Maniscalco
2024-09-06 20:11 ` Akhil P Oommen
2024-09-09 15:08 ` Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 08/10] drm/msm/A6XX: Add a flag to allow preemption to submitqueue_create Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 09/10] drm/msm/A6xx: Enable preemption for A750 Antonino Maniscalco
2024-09-05 14:51 ` [PATCH v3 10/10] Documentation: document adreno preemption Antonino Maniscalco
2024-09-06 19:58 ` [PATCH v3 00/10] Preemption support for A7XX Akhil P Oommen
2024-09-09 15:36 ` Rob Clark
2024-09-12 13:49 ` Antonino Maniscalco
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