Re: [PATCH v2] riscv: hwprobe: export Zicntr and Zihpm extensions

[Conor Dooley <conor.dooley@microchip.com>]

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On Thu, Sep 05, 2024 at 09:40:14AM +0200, Miquel Sabaté Solà wrote:
> On dt., d’ag. 20 2024, Miquel Sabaté Solà wrote:
> 
> > Export Zicntr and Zihpm ISA extensions through the hwprobe syscall.
> >
> > Signed-off-by: Miquel Sabaté Solà <mikisabate@gmail.com>
> > ---
> >  Documentation/arch/riscv/hwprobe.rst  | 6 ++++++
> >  arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> >  arch/riscv/kernel/sys_hwprobe.c       | 2 ++
> >  3 files changed, 10 insertions(+)
> >
> > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > index 3db60a0911df..cfd2929d0562 100644
> > --- a/Documentation/arch/riscv/hwprobe.rst
> > +++ b/Documentation/arch/riscv/hwprobe.rst
> > @@ -183,6 +183,9 @@ The following keys are defined:
> >         defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
> >         from commit 5059e0ca641c ("update to ratified").
> >  
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
> > +       is supported as defined in the RISC-V ISA manual.
> > +
> >    * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
> >         defined in the RISC-V Integer Conditional (Zicond) operations extension
> >         manual starting from commit 95cf1f9 ("Add changes requested by Ved
> > @@ -192,6 +195,9 @@ The following keys are defined:
> >         supported as defined in the RISC-V ISA manual starting from commit
> >         d8ab5c78c207 ("Zihintpause is ratified").
> >  
> > +  * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
> > +       is supported as defined in the RISC-V ISA manual.
> > +
> >    * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
> >      supported, as defined by version 1.0 of the RISC-V Vector extension manual.
> >  
> > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> > index b706c8e47b02..098a815b3fd4 100644
> > --- a/arch/riscv/include/uapi/asm/hwprobe.h
> > +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> > @@ -72,6 +72,8 @@ struct riscv_hwprobe {
> >  #define		RISCV_HWPROBE_EXT_ZCF		(1ULL << 46)
> >  #define		RISCV_HWPROBE_EXT_ZCMOP		(1ULL << 47)
> >  #define		RISCV_HWPROBE_EXT_ZAWRS		(1ULL << 48)
> > +#define		RISCV_HWPROBE_EXT_ZICNTR	(1ULL << 49)
> > +#define		RISCV_HWPROBE_EXT_ZIHPM		(1ULL << 50)
> >  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
> >  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
> >  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
> > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> > index 8d1b5c35d2a7..910b41b6a7ab 100644
> > --- a/arch/riscv/kernel/sys_hwprobe.c
> > +++ b/arch/riscv/kernel/sys_hwprobe.c
> > @@ -107,9 +107,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> >  		EXT_KEY(ZCB);
> >  		EXT_KEY(ZCMOP);
> >  		EXT_KEY(ZICBOZ);
> > +		EXT_KEY(ZICNTR);
> >  		EXT_KEY(ZICOND);
> >  		EXT_KEY(ZIHINTNTL);
> >  		EXT_KEY(ZIHINTPAUSE);
> > +		EXT_KEY(ZIHPM);
> >  		EXT_KEY(ZIMOP);
> >  		EXT_KEY(ZKND);
> >  		EXT_KEY(ZKNE);
> >
> > base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9
> 
> Hello,
> 
> Can I get a review on this version of this patchset?

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

By the way, I totally missed this first time around because the v2 was
sent as a reply to v1 - it's pretty common for people to view their
mailbox sorted by thread, and sending new versions as a reply will bury
it.

Cheers,
Conor.

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