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However, only one of the core types may be active at a given time, and to software, it appears as logical cores that could switch between P-mode and E-mode, depending on the p-state. Unforunately, only the performance cores can execute 32-bit EL0. To software, this results in logical cores that lose ability to execute 32-bit EL0 when the p-state is below a certain value. Since these CPU cores only supported 16K pages, many AArch32 executables will not run anyways. This series disables 32-bit EL0 for these SoCs. Changes since v1: - Drop #ifdef CONFIG_ARCH_APPLE, the code to disable NV1 on M2 does not use it either. - Added comment to explain why 32-bit EL0 have to be disabled. v1: https://lore.kernel.org/asahi/20240906171449.324354-1-towinchenmi@gmail.com Nick Chan --- Nick Chan (2): arm64: cputype: Add CPU types for A7-A11, T2 SoCs arm64: cpufeature: Pretend that Apple A10 family does not support 32-bit EL0 arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++--------- arch/arm64/kernel/cpufeature.c | 27 ++++++++++++++++++++ 2 files changed, 57 insertions(+), 12 deletions(-) base-commit: 9aaeb87ce1e966169a57f53a02ba05b30880ffb8 -- 2.46.0