From: Billy Tsai <billy_tsai@aspeedtech.com>
To: <linus.walleij@linaro.org>, <brgl@bgdev.pl>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>,
<andrew@codeconstruct.com.au>, <linux-gpio@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
<BMC-SW@aspeedtech.com>, <Peter.Yin@quantatw.com>,
<Jay_Zhang@wiwynn.com>
Subject: [PATCH v4 0/6] Add Aspeed G7 gpio support
Date: Thu, 19 Sep 2024 17:43:33 +0800 [thread overview]
Message-ID: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> (raw)
The Aspeed 7th generation SoC features two GPIO controllers: one with 12
GPIO pins and another with 216 GPIO pins. The main difference from the
previous generation is that the control logic has been updated to support
per-pin control, allowing each pin to have its own 32-bit register for
configuring value, direction, interrupt type, and more.
This patch serial also add low-level operations (llops) to abstract the
register access for GPIO registers and the coprocessor request/release in
gpio-aspeed.c making it easier to extend the driver to support different
hardware register layouts.
Change since v3:
- Add `privilege_ctrl` and `privilege_init` callback
- Use `bool aspeed_gpio_support_copro()` api to replace the
`cmd_source_supoort` flag
- Add the `dcache_require` flag and move the dcache usage into the
reg_bit_set callback
- `reg_bits_set` -> `reg_bit_set` and `reg_bits_read` -> `reg_bits_get`
- `bool copro = 0` -> `bool copro = false`
- `if (!gpio->config->llops->reg_bit_set ||
!gpio->config->llops->reg_bits_get) return -EINVAL;`
- Correct the access of reg_irq_status
- Remove __init attribute to fix the compiler warning
Change since v2:
- Correct minItems for gpio-line names
- Remove the example for ast2700, because it’s the same as the AST2600
- Fix the sparse warning which is reported by the test robot
- Remove the version and use the match data to replace it.
- Add another two patches one for deferred probe one for flush write.
Changes since v1:
- Merge the gpio-aspeed-g7.c into the gpio-aspeed.c.
- Create the llops in gpio-aspeed.c for flexibility.
Billy Tsai (6):
dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700
gpio: aspeed: Remove the name for bank array
gpio: aspeed: Create llops to handle hardware access
gpio: aspeed: Support G7 Aspeed gpio controller
gpio: aspeed: Change the macro to support deferred probe
gpio: aspeed: Add the flush write to ensure the write complete.
.../bindings/gpio/aspeed,ast2400-gpio.yaml | 19 +-
drivers/gpio/gpio-aspeed.c | 565 +++++++++++-------
2 files changed, 358 insertions(+), 226 deletions(-)
--
2.25.1
next reply other threads:[~2024-09-19 9:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-19 9:43 Billy Tsai [this message]
2024-09-19 9:43 ` [PATCH v4 1/6] dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700 Billy Tsai
2024-09-19 9:43 ` [PATCH v4 2/6] gpio: aspeed: Remove the name for bank array Billy Tsai
2024-09-19 9:43 ` [PATCH v4 3/6] gpio: aspeed: Create llops to handle hardware access Billy Tsai
2024-09-20 2:56 ` Andrew Jeffery
2024-09-20 9:19 ` Billy Tsai
2024-09-23 0:34 ` Andrew Jeffery
2024-09-23 2:20 ` Billy Tsai
2024-09-19 9:43 ` [PATCH v4 4/6] gpio: aspeed: Support G7 Aspeed gpio controller Billy Tsai
2024-09-19 9:43 ` [PATCH v4 5/6] gpio: aspeed: Change the macro to support deferred probe Billy Tsai
2024-09-19 9:43 ` [PATCH v4 6/6] gpio: aspeed: Add the flush write to ensure the write complete Billy Tsai
2024-10-01 14:18 ` Linus Walleij
2024-10-02 10:27 ` Bartosz Golaszewski
2024-10-02 15:09 ` Billy Tsai
2024-10-02 15:48 ` Bartosz Golaszewski
2024-10-02 17:02 ` Billy Tsai
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