From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 021BA7DA76 for ; Fri, 20 Sep 2024 11:23:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726831438; cv=none; b=oMb9cnook3Qo/zy+BLBSkvWQccgX0eV8EG2hGwz9ReTPG95LqbQRkUk+dn11PJxbpwH10fCjxXPPEbAzD3ssii6HoXNQnnriRWCRrqcvlTk2U/0QwclpGsmAPlfYbr7mMmCFrGNvdNr9XzGeLGKSSyajYiIKn3Kw885KTcYJfU4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726831438; c=relaxed/simple; bh=AkM238QRWy+ApukMPpqLoxeNHLgL+v1nKMPRGOAfscM=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=oQcxJCRLdHZyO/U78mWhzTWoavfWLyYTNh6HnNJzDDbeh+Y/r0g/opQ/URnB2qjJmBih3W6wXnpUOedjqciJnqwNcJ5SeuzueTo/+5y34AN2F1yrRZEqnGoceAKaAjtdd8A/T8wuKGbx8I/eNcptjVALJQNHYHtCR5fpVLhZCzA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=k9VfDdAI; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="k9VfDdAI" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 48KANihQ015956; Fri, 20 Sep 2024 04:23:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pfpt0220; bh=XC5QVxcGw5NnMFktTUGqoKe FvDCdh3rMuwuC6VCuzIg=; b=k9VfDdAIyI6jnPmiVxOnJRIThoFZYQZNsNtgrew EXsgtFh8eZhvU60XbOVP9gllaiW6lEIS9dsvVPmoE5n+cDD/IG4gGrxN9AJvu9j2 X3j+H6iT7+Fc1mmyhbOONHLjfRdnGTho+B/egd4L0odLElNWmeqwtEtzy5VweIab pzIgEQNNvC/ZSZrp58HqSGw62WqhnI7aLn0b1qluXDlTYpsMASqQvGVgYCZgFpZs fglvxBj8i39/VKrWIwLKPxkfwhrZg1ktyrgytjK/MBlMFQ8hK49oJuFUDskSMIYX JBM4VveaV/HY7dYzdDJWhMLnXDZtxFOQINbbkP0zG10ZuJg== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 41s78rg6m1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Sep 2024 04:23:30 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 20 Sep 2024 04:23:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 20 Sep 2024 04:23:29 -0700 Received: from localhost.localdomain (unknown [10.29.37.241]) by maili.marvell.com (Postfix) with ESMTP id 6697E5B6921; Fri, 20 Sep 2024 04:23:25 -0700 (PDT) From: Anshumali Gaur To: , , , , , , , , , , CC: Anshumali Gaur Subject: [PATCH 0/4] soc: marvell: Add a general purpose RVU physical Date: Fri, 20 Sep 2024 16:53:14 +0530 Message-ID: <20240920112318.2722488-1-agaur@marvell.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: aoa1b_FSsOfBUAZ2UI_EcdAdpO1eQBZk X-Proofpoint-GUID: aoa1b_FSsOfBUAZ2UI_EcdAdpO1eQBZk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 Resource virtualization unit (RVU) on Marvell's Octeon series of silicons maps HW resources from the network, crypto and other functional blocks into PCI-compatible physical and virtual functions. Each functional block again has multiple local functions (LFs) for provisioning to PCI devices. RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs). And RVU admin function (AF) is the one which manages all the resources (local functions etc) in the system. Functionality of these PFs and VFs depends on which block LFs are attached to them. Depending on usecase some PFs might support IO (ie LFs attached) and some may not. For the usecases where PF doesn't (need to) support IO, PF's driver will be limited to below functionality. 1. Creating and destroying of PCIe SRIOV VFs 2. Support mailbox communication between VFs and admin function (RVU AF) 3. PCIe Function level reset (FLR) for VFs For such PFs, this patch series adds a general purpose driver which supports above functionality. This will avoid duplicating same functionality for different RVU PFs. Next generation of Octeon silicon will have many new RVU blocks added. Eg: ML, Octeon (connected as an EP card) to host network packet path etc For such functionality there could be only userspace VF drivers hence a generic PF driver in Kernel is needed to support these VF drivers. For reference RVU AF driver is at drivers/net/ethernet/marvell/octeontx2/af/ Example RVU PF drivers drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c Example RVU VF drivers drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c Patch-1: This patch adds a generic PF driver with probe() and sriov() capabilities. Patch-2: This patch adds PF-AF mailbox support to the generic PF driver. Patch-3: This patch adds PF-VF mailbox support to the generic PF driver. Patch-4: This patch adds FLR handler to the generic PF driver. Anshumali Gaur (4): soc: marvell: Add a general purpose RVU PF driver soc: marvell: rvu-pf: Add PF to AF mailbox communication support. soc: marvell: rvu-pf: Add mailbox communication btw RVU VFs and PF. soc: marvell: rvu-pf: Handle function level reset (FLR) IRQs for VFs drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/marvell/Kconfig | 19 + drivers/soc/marvell/Makefile | 2 + drivers/soc/marvell/rvu_gen_pf/Makefile | 5 + drivers/soc/marvell/rvu_gen_pf/gen_pf.c | 1087 +++++++++++++++++++++++ drivers/soc/marvell/rvu_gen_pf/gen_pf.h | 152 ++++ 7 files changed, 1267 insertions(+) create mode 100644 drivers/soc/marvell/Kconfig create mode 100644 drivers/soc/marvell/Makefile create mode 100644 drivers/soc/marvell/rvu_gen_pf/Makefile create mode 100644 drivers/soc/marvell/rvu_gen_pf/gen_pf.c create mode 100644 drivers/soc/marvell/rvu_gen_pf/gen_pf.h -- 2.25.1