From: Antonino Maniscalco <antomani103@gmail.com>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Jonathan Corbet <corbet@lwn.net>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org,
Antonino Maniscalco <antomani103@gmail.com>,
Neil Armstrong <neil.armstrong@linaro.org>
Subject: [PATCH v5 04/11] drm/msm: Add CONTEXT_SWITCH_CNTL bitfields
Date: Tue, 24 Sep 2024 13:30:39 +0200 [thread overview]
Message-ID: <20240924-preemption-a750-t-v5-4-0be2bf81c187@gmail.com> (raw)
In-Reply-To: <20240924-preemption-a750-t-v5-0-0be2bf81c187@gmail.com>
Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml.
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8450-HDK
Signed-off-by: Antonino Maniscalco <antomani103@gmail.com>
---
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc1034f6b7a2e41 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -1337,7 +1337,12 @@ to upconvert to 32b float internally?
<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
</array>
- <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
+ <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL">
+ <bitfield name="STOP" pos="0" type="boolean"/>
+ <bitfield name="LEVEL" low="6" high="7"/>
+ <bitfield name="USES_GMEM" pos="8" type="boolean"/>
+ <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/>
+ </reg32>
<reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
--
2.46.1
next prev parent reply other threads:[~2024-09-24 11:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-24 11:30 [PATCH v5 00/11] Preemption support for A7XX Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 01/11] drm/msm: Fix bv_fence being used as bv_rptr Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 02/11] drm/msm/A6XX: Track current_ctx_seqno per ring Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 03/11] drm/msm: Add a `preempt_record_size` field Antonino Maniscalco
2024-09-24 11:30 ` Antonino Maniscalco [this message]
2024-09-24 11:30 ` [PATCH v5 05/11] drm/msm/A6xx: Implement preemption for A7XX targets Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 06/11] drm/msm/A6xx: Sync relevant adreno_pm4.xml changes Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 07/11] drm/msm/A6xx: Use posamble to reset counters on preemption Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 08/11] drm/msm/A6xx: Add traces for preemption Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 09/11] drm/msm/A6XX: Add a flag to allow preemption to submitqueue_create Antonino Maniscalco
2024-09-24 11:30 ` [PATCH v5 10/11] drm/msm/A6xx: Enable preemption for A750 Antonino Maniscalco
2024-09-24 16:27 ` Rob Clark
2024-09-24 11:30 ` [PATCH v5 11/11] Documentation: document adreno preemption Antonino Maniscalco
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