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charset=us-ascii Content-Disposition: inline tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: 9852d85ec9d492ebef56dc5f229416c925758edc commit: f862bbf4cdca696ef3073c5cf3d340b778a3e42a riscv: Allow NOMMU kernels to run in S-mode date: 6 months ago config: riscv-randconfig-r064-20240930 (https://download.01.org/0day-ci/archive/20240930/202409300745.CSqY0i4z-lkp@intel.com/config) compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240930/202409300745.CSqY0i4z-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202409300745.CSqY0i4z-lkp@intel.com/ All warnings (new ones prefixed by >>): >> arch/riscv/errata/andes/errata.c:53:14: warning: result of comparison of constant 9223372036854811205 with expression of type 'unsigned long' is always true [-Wtautological-constant-out-of-range-compare] if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) ~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~ 1 warning generated. vim +53 arch/riscv/errata/andes/errata.c e021ae7f5145d4 Lad Prabhakar 2023-08-18 40 ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 41 static void errata_probe_iocp(unsigned int stage, unsigned long arch_id, unsigned long impid) e021ae7f5145d4 Lad Prabhakar 2023-08-18 42 { ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 43 static bool done; ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 44 e021ae7f5145d4 Lad Prabhakar 2023-08-18 45 if (!IS_ENABLED(CONFIG_ERRATA_ANDES_CMO)) ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 46 return; ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 47 ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 48 if (done) ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 49 return; ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 50 ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 51 done = true; e021ae7f5145d4 Lad Prabhakar 2023-08-18 52 e021ae7f5145d4 Lad Prabhakar 2023-08-18 @53 if (arch_id != ANDESTECH_AX45MP_MARCHID || impid != ANDESTECH_AX45MP_MIMPID) ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 54 return; e021ae7f5145d4 Lad Prabhakar 2023-08-18 55 e021ae7f5145d4 Lad Prabhakar 2023-08-18 56 if (!ax45mp_iocp_sw_workaround()) ed5b7cfd7839f9 Lad Prabhakar 2023-11-30 57 return; e021ae7f5145d4 Lad Prabhakar 2023-08-18 58 e021ae7f5145d4 Lad Prabhakar 2023-08-18 59 /* Set this just to make core cbo code happy */ e021ae7f5145d4 Lad Prabhakar 2023-08-18 60 riscv_cbom_block_size = 1; e021ae7f5145d4 Lad Prabhakar 2023-08-18 61 riscv_noncoherent_supported(); e021ae7f5145d4 Lad Prabhakar 2023-08-18 62 } e021ae7f5145d4 Lad Prabhakar 2023-08-18 63 :::::: The code at line 53 was first introduced by commit :::::: e021ae7f5145d46ab64cb058cbffda31059f37e5 riscv: errata: Add Andes alternative ports :::::: TO: Lad Prabhakar :::::: CC: Palmer Dabbelt -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki