From: Borislav Petkov <bp@alien8.de>
To: Jim Mattson <jmattson@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
Josh Poimboeuf <jpoimboe@kernel.org>,
Sandipan Das <sandipan.das@amd.com>,
Kai Huang <kai.huang@intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, Venkatesh Srinivas <venkateshs@chromium.org>
Subject: Re: [PATCH v4 1/3] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET
Date: Mon, 7 Oct 2024 16:30:19 +0200 [thread overview]
Message-ID: <20241007143019.GAZwPwe286itXE2Wj2@fat_crate.local> (raw)
In-Reply-To: <20240913173242.3271406-2-jmattson@google.com>
On Fri, Sep 13, 2024 at 10:32:27AM -0700, Jim Mattson wrote:
> AMD's initial implementation of IBPB did not clear the return address
> predictor. Beginning with Zen4, AMD's IBPB *does* clear the return
> address predictor. This behavior is enumerated by
> CPUID.80000008H:EBX.IBPB_RET[bit 30].
>
> Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID,
> when determining cross-vendor capabilities.
>
> Suggested-by: Venkatesh Srinivas <venkateshs@chromium.org>
> Signed-off-by: Jim Mattson <jmattson@google.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index cabd6b58e8ec..a222a24677d7 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -215,7 +215,7 @@
> #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* Disable Speculative Store Bypass. */
> #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* AMD SSBD implementation via LS_CFG MSR */
> #define X86_FEATURE_IBRS ( 7*32+25) /* "ibrs" Indirect Branch Restricted Speculation */
> -#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without RSB flush */
I see upstream
#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier */
Where does "without RSB flush" come from?
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2024-10-07 14:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-13 17:32 [PATCH v4 0/3] Distinguish between variants of IBPB Jim Mattson
2024-09-13 17:32 ` [PATCH v4 1/3] x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET Jim Mattson
2024-10-07 14:30 ` Borislav Petkov [this message]
2024-10-07 17:38 ` Jim Mattson
2024-09-13 17:32 ` [PATCH v4 2/3] KVM: x86: Advertise AMD_IBPB_RET to userspace Jim Mattson
2024-09-13 17:32 ` [PATCH v4 3/3] KVM: x86: AMD's IBPB is not equivalent to Intel's IBPB Jim Mattson
2024-09-27 18:52 ` [PATCH v4 0/3] Distinguish between variants of IBPB Jim Mattson
2024-09-30 16:19 ` Sean Christopherson
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