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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241007081543.3475027-1-quic_vpernami@quicinc.com> On Mon, Oct 07, 2024 at 01:45:41PM +0530, Vivek Pernamitta wrote: > Add MHI controller configuration for QDU100 device. > > This Qualcomm QDU100 device is inline accelerator card > which is an extension to QRU100 5G RAN platform. > which is designed to simplify 5G deployments by offering > a turnkey solution for ease of deployment with O-RAN > fronthaul and 5G NR layer 1 High (L1 High) processing, > and to accelerate operator and infrastructure vendor > adoption of virtualized RAN platforms. > > Currently IP_SW1/2 channel support is not present in > mhi_net driver, will be supporting them in future. I don't know what column width you are using, but please use 75 columns for patch descriptions. > > https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf > Signed-off-by: Vivek Pernamitta > > --- > changes from V1: > - Changing naming convention from modem_qcom_qdu100* > to mhi_qcom_qdu100* > - Added more commit test for IP_SW1/2 channels. > - Fixed and corrected by passing mhi_pci_dev_info struct > instead of mhi_controller_config. > --- > --- > drivers/bus/mhi/host/pci_generic.c | 60 ++++++++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > index 9938bb034c1c..b9b7dd8d9411 100644 > --- a/drivers/bus/mhi/host/pci_generic.c > +++ b/drivers/bus/mhi/host/pci_generic.c > @@ -245,6 +245,63 @@ struct mhi_pci_dev_info { > .channel = ch_num, \ > } > > +static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { > + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), > + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), > + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), > + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), > + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), > + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), > + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), > + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), > + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), > + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), > + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), > + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), > + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), > + MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6), > + MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6), > + MHI_CHANNEL_CONFIG_UL(50, "IP_SW2", 256, 7), > + MHI_CHANNEL_CONFIG_DL(51, "IP_SW2", 256, 7), Please drop these unsupported IP_SW channels until you add support in mhi-net driver. > +}; > + > +static struct mhi_event_config mhi_qcom_qdu100_events[] = { > + /* first ring is control+data ring */ > + MHI_EVENT_CONFIG_CTRL(0, 64), > + /* SAHARA dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(1, 256), > + /* Software channels dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(2, 64), > + MHI_EVENT_CONFIG_SW_DATA(3, 256), > + MHI_EVENT_CONFIG_SW_DATA(4, 256), > + /* Software IP channels dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(5, 512), > + MHI_EVENT_CONFIG_SW_DATA(6, 512), > + MHI_EVENT_CONFIG_SW_DATA(7, 512), > +}; > + > +static const struct mhi_controller_config mhi_qcom_qdu100_config = { > + .max_channels = 128, > + .timeout_ms = 120000, > + .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), > + .ch_cfg = mhi_qcom_qdu100_channels, > + .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), > + .event_cfg = mhi_qcom_qdu100_events, > +}; > + > +static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { > + .name = "qcom-lassen", I don't think you can use internal chip name in the drivers. Please use the actual chip code like QDU100. > + .fw = "qcom/lassen/xbl_s.melf", > + .edl = "qcom/lassen/edl.mbn", Could you please push these fw to linux-firmware repo? This is a requirement to get this patch accepted. I should've imposed this at the start itself... > + .edl_trigger = true, > + .config = &mhi_qcom_qdu100_config, > + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, > + .dma_data_width = 32, > + .sideband_wake = false, > +}; > + > static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { > MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), > MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), > @@ -822,6 +879,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { > /* NETPRISMA FCUN69 (SDX6X) */ > { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), > .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, > + /* QDU100, x100-DU */ > + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), > + .driver_data = (kernel_ulong_t)&mhi_qcom_qdu100_info }, Spare after (kernel_ulong_t) and also sort the entries as per the comment above mhi_pci_id_table[]. - Mani -- மணிவண்ணன் சதாசிவம்