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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241011104142.1181773-8-quic_qianyu@quicinc.com> On Fri, Oct 11, 2024 at 03:41:41AM -0700, Qiang Yu wrote: > Currently, the cfg_1_9_0 which is being used for X1E80100 has config_sid > callback in its ops and doesn't disable ASPM L0s. However, as same as > SC8280X, PCIe controllers on X1E80100 are connected to SMMUv3 and it is "...connected to SMMUv3, hence doesn't need config_sid() callback" > recommended to disable ASPM L0s. Hence reuse cfg_sc8280xp for X1E80100. "...and hardware team has recommended to disable L0s as it is broken in the controller." > > Fixes: 6d0c39324c5f ("PCI: qcom: Add X1E80100 PCIe support") > Signed-off-by: Qiang Yu Reviewed-by: Manivannan Sadhasivam We need to backport this patch to stable to fix the L0s handling. But we don't need the previous patch as even without that cfg_sc8280xp disables L0s. - Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 468bd4242e61..c533e6024ba2 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1847,7 +1847,7 @@ static const struct of_device_id qcom_pcie_match[] = { > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, > { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, > - { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, > + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, > { } > }; > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்