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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241012050611.1908-3-linux.amoon@gmail.com> On Sat, Oct 12, 2024 at 10:36:04AM +0530, Anand Moon wrote: > Refactor the reset control handling in the Rockchip PCIe driver, > introducing a more robust and efficient method for assert and > deassert reset controller using reset_control_bulk*() API. Using the > reset_control_bulk APIs, the reset handling for the core clocks reset > unit becomes much simpler. > Same comments as previous patch. > Spilt the reset controller in two groups as pre the RK3399 TRM. *per Also please state the TRM name and section for reference. > After power up, the software driver should de-assert the reset of PCIe PHY, > then wait the PLL locked by polling the status, if PLL > has locked, then can de-assert the reset simultaneously > driver need to De-assert the reset pins simultionaly. > > PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N. > > - replace devm_reset_control_get_exclusive() with > devm_reset_control_bulk_get_exclusive(). > - replace reset_control_assert with > reset_control_bulk_assert(). > - replace reset_control_deassert with > reset_control_bulk_deassert(). > > Signed-off-by: Anand Moon > --- > v7: replace devm_reset_control_bulk_get_optional_exclusive() > with devm_reset_control_bulk_get_exclusive() > update the functional changes. > V6: Add reason for the split of the RESET pins. > v5: Fix the De-assert reset core as per the TRM > De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N > simultaneously. > v4: use dev_err_probe in error path. > v3: Fix typo in commit message, dropped reported by. > v2: Fix compilation error reported by Intel test robot > fixed checkpatch warning. > --- > drivers/pci/controller/pcie-rockchip.c | 151 +++++-------------------- > drivers/pci/controller/pcie-rockchip.h | 26 +++-- > 2 files changed, 49 insertions(+), 128 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > index 2777ef0cb599..9a118e2b8cbd 100644 > --- a/drivers/pci/controller/pcie-rockchip.c > +++ b/drivers/pci/controller/pcie-rockchip.c > @@ -30,7 +30,7 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) [...] > + err = reset_control_bulk_assert(ROCKCHIP_NUM_PM_RSTS, > + rockchip->pm_rsts); > + if (err) > + return dev_err_probe(dev, err, "reset bulk assert pm reset\n"); 'Couldn't assert PM resets' > > for (i = 0; i < MAX_LANE_NUM; i++) { > err = phy_init(rockchip->phys[i]); > @@ -173,47 +128,17 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > } > } > > - err = reset_control_assert(rockchip->core_rst); > - if (err) { > - dev_err(dev, "assert core_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "assert mgmt_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_assert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "assert pipe_rst err %d\n", err); > - goto err_exit_phy; > - } > + err = reset_control_bulk_assert(ROCKCHIP_NUM_CORE_RSTS, > + rockchip->core_rsts); > + if (err) > + return dev_err_probe(dev, err, "reset bulk assert core reset\n"); 'Couldn't assert Core resets' > > udelay(10); > > - err = reset_control_deassert(rockchip->pm_rst); > - if (err) { > - dev_err(dev, "deassert pm_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->aclk_rst); > + err = reset_control_bulk_deassert(ROCKCHIP_NUM_PM_RSTS, > + rockchip->pm_rsts); > if (err) { > - dev_err(dev, "deassert aclk_rst err %d\n", err); > - goto err_exit_phy; > - } > - > - err = reset_control_deassert(rockchip->pclk_rst); > - if (err) { > - dev_err(dev, "deassert pclk_rst err %d\n", err); > + dev_err(dev, "reset bulk deassert pm err %d\n", err); 'Couldn't deassert PM resets' > goto err_exit_phy; > } > > @@ -256,31 +181,15 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > * Please don't reorder the deassert sequence of the following > * four reset pins. I don't think my earlier comment on this addressed. Why are you changing the reset order? Why can't you have the resets in below (older) order? static const char * const rockchip_pci_core_rsts[] = { mgmt-sticky", "core", "mgmt", "pipe", }; Also, this comment should be removed now. > */ > - err = reset_control_deassert(rockchip->mgmt_sticky_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->core_rst); > + err = reset_control_bulk_deassert(ROCKCHIP_NUM_CORE_RSTS, > + rockchip->core_rsts); > if (err) { > - dev_err(dev, "deassert core_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->mgmt_rst); > - if (err) { > - dev_err(dev, "deassert mgmt_rst err %d\n", err); > - goto err_power_off_phy; > - } > - > - err = reset_control_deassert(rockchip->pipe_rst); > - if (err) { > - dev_err(dev, "deassert pipe_rst err %d\n", err); > + dev_err(dev, "reset bulk deassert core err %d\n", err); 'Couldn't deassert Core resets' - Mani -- மணிவண்ணன் சதாசிவம்